Commit 2d6e9ee7 authored by Claudiu Beznea's avatar Claudiu Beznea
Browse files

clk: at91: sama7g5: Allocate only the needed amount of memory for PLLs 



The maximum number of PLL components on SAMA7G5 is 3 (one fractional
part and 2 dividers). Allocate the needed amount of memory for
sama7g5_plls 2d array. Previous code used to allocate 7 array entries for
each PLL. While at it, replace 3 with PLL_COMPID_MAX in the loop which
parses the sama7g5_plls 2d array.

Fixes: cb783bbb ("clk: at91: sama7g5: add clock support for sama7g5")
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20240714141315.19480-1-claudiu.beznea@tuxon.dev


Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@tuxon.dev>
parent 33013b43

drivers/clk/at91/sama7g5.c

+3 −2
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ enum pll_component_id { 
	PLL_COMPID_FRAC,

	PLL_COMPID_DIV0,

	PLL_COMPID_DIV1,

	PLL_COMPID_MAX,

};



/*
@@ -157,7 +158,7 @@ static struct sama7g5_pll { 
	u8 t;

	u8 eid;

	u8 safe_div;

} sama7g5_plls[][PLL_ID_MAX] = {

} sama7g5_plls[][PLL_COMPID_MAX] = {

	[PLL_ID_CPU] = {

		[PLL_COMPID_FRAC] = {

			.n = "cpupll_fracck",
@@ -1030,7 +1031,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) 
	sama7g5_pmc->chws[PMC_MAIN] = hw;



	for (i = 0; i < PLL_ID_MAX; i++) {

		for (j = 0; j < 3; j++) {

		for (j = 0; j < PLL_COMPID_MAX; j++) {

			struct clk_hw *parent_hw;



			if (!sama7g5_plls[i][j].n)