Commit 2d945dde authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk updates from Stephen Boyd:
 "This is the usual collection of primarily clk driver updates.

  The big part of the diff is all the new Qualcomm clk drivers added for
  a few SoCs they're working on. The other two vendors with significant
  work this cycle are Renesas and Amlogic. Renesas adds a bunch of clks
  to existing drivers and supports some new SoCs while Amlogic is
  starting a significant refactoring to simplify their code.

  The core framework gained a pair of helpers to get the 'struct device'
  or 'struct device_node' associated with a 'struct clk_hw'. Some
  associated KUnit tests were added for these simple helpers as well.

  Beyond that core change there are lots of little fixes throughout the
  clk drivers for the stuff we see every day, wrong clk driver data that
  affects tree topology or supported frequencies, etc. They're not found
  until the clks are actually used by some consumer device driver.

  New Drivers:
   - Global, display, gpu, video, camera, tcsr, and rpmh clock
     controller for the Qualcomm Milos SoC
   - Camera, display, GPU, and video clock controllers for Qualcomm
     QCS615
   - Video clock controller driver for Qualcomm SM6350
   - Camera clock controller driver for Qualcomm SC8180X
   - I3C clocks and resets on Renesas RZ/G3E
   - Expanded Serial Peripheral Interface (xSPI) clocks and resets on
     Renesas RZ/V2H(P) and RZ/V2N
   - SPI (RSPI) clocks and resets on Renesas RZ/V2H(P)
   - SDHI and I2C clocks on Renesas RZ/T2H and RZ/N2H
   - Ethernet clocks and resets on Renesas RZ/G3E
   - Initial support for the Renesas RZ/T2H (R9A09G077) and RZ/N2H
     (R9A09G087) SoCs
   - Ethernet clocks and resets on Renesas RZ/V2H and RZ/V2N
   - Timer, I2C, watchdog, GPU, and USB2.0 clocks and resets on Renesas
     RZ/V2N

  Updates:
   - Support atomic PWMs in the PWM clk driver
   - clk_hw_get_dev() and clk_hw_get_of_node() helpers
   - Replace round_rate() with determine_rate() in various clk drivers
   - Convert clk DT bindings to DT schema format for DT validation
   - Various clk driver cleanups and refactorings from static analysis
     tools and possibly real humans
   - A lot of little fixes here and there to things like clk tree
     topology, missing frequencies, flagging clks as critical, etc"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (216 commits)
  clk: clocking-wizard: Fix the round rate handling for versal
  clk: Fix typos
  clk: spacemit: ccu_pll: fix error return value in recalc_rate callback
  clk: tegra: periph: Make tegra_clk_periph_ops static
  clk: tegra: periph: Fix error handling and resolve unsigned compare warning
  clk: imx: scu: convert from round_rate() to determine_rate()
  clk: imx: pllv4: convert from round_rate() to determine_rate()
  clk: imx: pllv3: convert from round_rate() to determine_rate()
  clk: imx: pllv2: convert from round_rate() to determine_rate()
  clk: imx: pll14xx: convert from round_rate() to determine_rate()
  clk: imx: pfd: convert from round_rate() to determine_rate()
  clk: imx: frac-pll: convert from round_rate() to determine_rate()
  clk: imx: fracn-gppll: convert from round_rate() to determine_rate()
  clk: imx: fixup-div: convert from round_rate() to determine_rate()
  clk: imx: cpu: convert from round_rate() to determine_rate()
  clk: imx: busy: convert from round_rate() to determine_rate()
  clk: imx: composite-93: remove round_rate() in favor of determine_rate()
  clk: imx: composite-8m: remove round_rate() in favor of determine_rate()
  clk: qcom: Remove redundant pm_runtime_mark_last_busy() calls
  clk: imx: Remove redundant pm_runtime_mark_last_busy() calls
  ...
parents be413ec7 64c21f25

Documentation/devicetree/bindings/clock/alphascale,acc.txt

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Alphascale Clock Controller



The ACC (Alphascale Clock Controller) is responsible for choosing proper

clock source, setting dividers and clock gates.



Required properties for the ACC node:

 - compatible: must be "alphascale,asm9260-clock-controller"

 - reg: must contain the ACC register base and size

 - #clock-cells : shall be set to 1.



Simple one-cell clock specifier format is used, where the only cell is used

as an index of the clock inside the provider.

It is encouraged to use dt-binding for clock index definitions. SoC specific

dt-binding should be included to the device tree descriptor. For example

Alphascale ASM9260:

#include <dt-bindings/clock/alphascale,asm9260.h>



This binding contains two types of clock providers:

 _AHB_ - AHB gate;

 _SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider.

All clock specific details can be found in the SoC documentation.

CLKID_AHB_ROM		0

CLKID_AHB_RAM		1

CLKID_AHB_GPIO		2

CLKID_AHB_MAC		3

CLKID_AHB_EMI		4

CLKID_AHB_USB0		5

CLKID_AHB_USB1		6

CLKID_AHB_DMA0		7

CLKID_AHB_DMA1		8

CLKID_AHB_UART0		9

CLKID_AHB_UART1		10

CLKID_AHB_UART2		11

CLKID_AHB_UART3		12

CLKID_AHB_UART4		13

CLKID_AHB_UART5		14

CLKID_AHB_UART6		15

CLKID_AHB_UART7		16

CLKID_AHB_UART8		17

CLKID_AHB_UART9		18

CLKID_AHB_I2S0		19

CLKID_AHB_I2C0		20

CLKID_AHB_I2C1		21

CLKID_AHB_SSP0		22

CLKID_AHB_IOCONFIG	23

CLKID_AHB_WDT		24

CLKID_AHB_CAN0		25

CLKID_AHB_CAN1		26

CLKID_AHB_MPWM		27

CLKID_AHB_SPI0		28

CLKID_AHB_SPI1		29

CLKID_AHB_QEI		30

CLKID_AHB_QUADSPI0	31

CLKID_AHB_CAMIF		32

CLKID_AHB_LCDIF		33

CLKID_AHB_TIMER0	34

CLKID_AHB_TIMER1	35

CLKID_AHB_TIMER2	36

CLKID_AHB_TIMER3	37

CLKID_AHB_IRQ		38

CLKID_AHB_RTC		39

CLKID_AHB_NAND		40

CLKID_AHB_ADC0		41

CLKID_AHB_LED		42

CLKID_AHB_DAC0		43

CLKID_AHB_LCD		44

CLKID_AHB_I2S1		45

CLKID_AHB_MAC1		46



CLKID_SYS_CPU		47

CLKID_SYS_AHB		48

CLKID_SYS_I2S0M		49

CLKID_SYS_I2S0S		50

CLKID_SYS_I2S1M		51

CLKID_SYS_I2S1S		52

CLKID_SYS_UART0		53

CLKID_SYS_UART1		54

CLKID_SYS_UART2		55

CLKID_SYS_UART3		56

CLKID_SYS_UART4		56

CLKID_SYS_UART5		57

CLKID_SYS_UART6		58

CLKID_SYS_UART7		59

CLKID_SYS_UART8		60

CLKID_SYS_UART9		61

CLKID_SYS_SPI0		62

CLKID_SYS_SPI1		63

CLKID_SYS_QUADSPI	64

CLKID_SYS_SSP0		65

CLKID_SYS_NAND		66

CLKID_SYS_TRACE		67

CLKID_SYS_CAMM		68

CLKID_SYS_WDT		69

CLKID_SYS_CLKOUT	70

CLKID_SYS_MAC		71

CLKID_SYS_LCD		72

CLKID_SYS_ADCANA	73



Example of clock consumer with _SYS_ and _AHB_ sinks.

uart4: serial@80010000 {

	compatible = "alphascale,asm9260-uart";

	reg = <0x80010000 0x4000>;

	clocks = <&acc CLKID_SYS_UART4>, <&acc CLKID_AHB_UART4>;

	interrupts = <19>;

};



Clock consumer with only one, _AHB_ sink.

timer0: timer@80088000 {

	compatible = "alphascale,asm9260-timer";

	reg = <0x80088000 0x4000>;

	clocks = <&acc CLKID_AHB_TIMER0>;

	interrupts = <29>;

};

Documentation/devicetree/bindings/clock/alphascale,asm9260-clock-controller.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/alphascale,asm9260-clock-controller.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Alphascale Clock Controller



maintainers:

  - Oleksij Rempel <linux@rempel-privat.de>



description: |

  The ACC (Alphascale Clock Controller) is responsible for choosing proper

  clock source, setting dividers and clock gates.



  Simple one-cell clock specifier format is used, where the only cell is used

  as an index of the clock inside the provider.

  It is encouraged to use dt-binding for clock index definitions. SoC specific

  dt-binding should be included to the device tree descriptor. For example

  Alphascale ASM9260:



  #include <dt-bindings/clock/alphascale,asm9260.h>



  This binding contains two types of clock providers:



    _AHB_ - AHB gate;

    _SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider.



  All clock specific details can be found in the SoC documentation.



properties:

  compatible:

    const: alphascale,asm9260-clock-controller



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



  clocks:

    maxItems: 1



required:

  - compatible

  - reg

  - '#clock-cells'



additionalProperties: false

Documentation/devicetree/bindings/clock/apm,xgene-device-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/apm,xgene-device-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: APM X-Gene SoC device clocks



maintainers:

  - Khuong Dinh <khuong@os.amperecomputing.com>



properties:

  compatible:

    const: apm,xgene-device-clock



  reg:

    minItems: 1

    maxItems: 2



  reg-names:

    items:

      - enum: [ csr-reg, div-reg ]

      - const: div-reg

    minItems: 1



  clocks:

    maxItems: 1



  "#clock-cells":

    const: 1



  clock-output-names:

    maxItems: 1



  clock-names:

    maxItems: 1



  csr-offset:

    description: Offset to the CSR reset register

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 0



  csr-mask:

    description: CSR reset mask bit

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 0xf



  enable-offset:

    description: Offset to the enable register

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 8



  enable-mask:

    description: CSR enable mask bit

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 0xf



  divider-offset:

    description: Offset to the divider register

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 0



  divider-width:

    description: Width of the divider register

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 0



  divider-shift:

    description: Bit shift of the divider register

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 0



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'

  - clock-output-names



additionalProperties: false

Documentation/devicetree/bindings/clock/apm,xgene-socpll-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/apm,xgene-socpll-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: APM X-Gene SoC PLL, PCPPLL, and PMD clocks



maintainers:

  - Khuong Dinh <khuong@os.amperecomputing.com>



properties:

  compatible:

    items:

      - enum:

          - apm,xgene-pcppll-clock

          - apm,xgene-pcppll-v2-clock

          - apm,xgene-pmd-clock

          - apm,xgene-socpll-clock

          - apm,xgene-socpll-v2-clock



  reg:

    maxItems: 1



  reg-names:

    items:

      - enum: [ csr-reg, div-reg ]

      - const: div-reg

    minItems: 1



  clocks:

    maxItems: 1



  clock-names:

    enum: [ pcppll, socpll ]



  "#clock-cells":

    const: 1



  clock-output-names:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'

  - clock-output-names



additionalProperties: false

Documentation/devicetree/bindings/clock/armada3700-periph-clock.txt

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* Peripheral Clock bindings for Marvell Armada 37xx SoCs



Marvell Armada 37xx SoCs provide peripheral clocks which are

used as clock source for the peripheral of the SoC.



There are two different blocks associated to north bridge and south

bridge.



The peripheral clock consumer should specify the desired clock by

having the clock ID in its "clocks" phandle cell.



The following is a list of provided IDs for Armada 3700 North bridge clocks:

ID	Clock name	Description

-----------------------------------

0	mmc		MMC controller

1	sata_host	Sata Host

2	sec_at		Security AT

3	sac_dap		Security DAP

4	tsecm		Security Engine

5	setm_tmx	Serial Embedded Trace Module

6	avs		Adaptive Voltage Scaling

7	sqf		SPI

8	pwm		PWM

9	i2c_2		I2C 2

10	i2c_1		I2C 1

11	ddr_phy		DDR PHY

12	ddr_fclk	DDR F clock

13	trace		Trace

14	counter		Counter

15	eip97		EIP 97

16	cpu		CPU



The following is a list of provided IDs for Armada 3700 South bridge clocks:

ID	Clock name	Description

-----------------------------------

0	gbe-50		50 MHz parent clock for Gigabit Ethernet

1	gbe-core	parent clock for Gigabit Ethernet core

2	gbe-125		125 MHz parent clock for Gigabit Ethernet

3	gbe1-50		50 MHz clock for Gigabit Ethernet port 1

4	gbe0-50		50 MHz clock for Gigabit Ethernet port 0

5	gbe1-125	125 MHz clock for Gigabit Ethernet port 1

6	gbe0-125	125 MHz clock for Gigabit Ethernet port 0

7	gbe1-core	Gigabit Ethernet core port 1

8	gbe0-core	Gigabit Ethernet core port 0

9	gbe-bm		Gigabit Ethernet Buffer Manager

10	sdio		SDIO

11	usb32-sub2-sys	USB 2 clock

12	usb32-ss-sys	USB 3 clock

13	pcie		PCIe controller



Required properties:



- compatible : shall be "marvell,armada-3700-periph-clock-nb" for the

  north bridge block, or

  "marvell,armada-3700-periph-clock-sb" for the south bridge block

- reg : must be the register address of North/South Bridge Clock register

- #clock-cells : from common clock binding; shall be set to 1



- clocks : list of the parent clock phandle in the following order:

  TBG-A P, TBG-B P, TBG-A S, TBG-B S and finally the xtal clock.





Example:



nb_perih_clk: nb-periph-clk@13000{

	compatible = "marvell,armada-3700-periph-clock-nb";

	reg = <0x13000 0x1000>;

	clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,

	<&tbg 3>, <&xtalclk>;

	#clock-cells = <1>;

};