Commit 2d95d132 authored by Michael Walle's avatar Michael Walle Committed by Pratyush Yadav
Browse files

mtd: spi-nor: get rid of SPI_NOR_NO_FR 



The Everspin FRAM devices are the only user of the NO_FR flag. Drop the
global flag and instead use a manufacturer fixup for the Everspin
flashes to drop the fast read support.

Signed-off-by: default avatarMichael Walle <mwalle@kernel.org>
Reviewed-by: default avatarTudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: default avatarPratyush Yadav <pratyush@kernel.org>
[pratyush@kernel.org: s/evervision/everspin/g in code and commit message]
Signed-off-by: default avatarPratyush Yadav <pratyush@kernel.org>
Link: https://lore.kernel.org/r/20240419141249.609534-5-mwalle@kernel.org
parent d323a418

drivers/mtd/spi-nor/core.c

+2 −7
Original line number Diff line number Diff line
@@ -2923,15 +2923,10 @@ static void spi_nor_init_default_params(struct spi_nor *nor) 
	params->page_size = info->page_size ?: SPI_NOR_DEFAULT_PAGE_SIZE;

	params->n_banks = info->n_banks ?: SPI_NOR_DEFAULT_N_BANKS;



	if (!(info->flags & SPI_NOR_NO_FR)) {

		/* Default to Fast Read for DT and non-DT platform devices. */

	/* Default to Fast Read for non-DT and enable it if requested by DT. */

	if (!np || of_property_read_bool(np, "m25p,fast-read"))

		params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;



		/* Mask out Fast Read if not requested at DT instantiation. */

		if (np && !of_property_read_bool(np, "m25p,fast-read"))

			params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;

	}



	/* (Fast) Read settings. */

	params->hwcaps.mask |= SNOR_HWCAPS_READ;

	spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],

drivers/mtd/spi-nor/core.h

+0 −2
Original line number Diff line number Diff line
@@ -470,7 +470,6 @@ struct spi_nor_id { 
 *                            Usually these will power-up in a write-protected

 *                            state.

 *   SPI_NOR_NO_ERASE:        no erase command needed.

 *   SPI_NOR_NO_FR:           can't do fastread.

 *   SPI_NOR_QUAD_PP:         flash supports Quad Input Page Program.

 *   SPI_NOR_RWW:             flash supports reads while write.

 *
@@ -519,7 +518,6 @@ struct flash_info { 
#define SPI_NOR_BP3_SR_BIT6		BIT(4)

#define SPI_NOR_SWP_IS_VOLATILE		BIT(5)

#define SPI_NOR_NO_ERASE		BIT(6)

#define SPI_NOR_NO_FR			BIT(7)

#define SPI_NOR_QUAD_PP			BIT(8)

#define SPI_NOR_RWW			BIT(9)

drivers/mtd/spi-nor/everspin.c

+15 −4
Original line number Diff line number Diff line
@@ -14,28 +14,39 @@ static const struct flash_info everspin_nor_parts[] = { 
		.size = SZ_16K,

		.sector_size = SZ_16K,

		.addr_nbytes = 2,

		.flags = SPI_NOR_NO_ERASE | SPI_NOR_NO_FR,

		.flags = SPI_NOR_NO_ERASE,

	}, {

		.name = "mr25h256",

		.size = SZ_32K,

		.sector_size = SZ_32K,

		.addr_nbytes = 2,

		.flags = SPI_NOR_NO_ERASE | SPI_NOR_NO_FR,

		.flags = SPI_NOR_NO_ERASE,

	}, {

		.name = "mr25h10",

		.size = SZ_128K,

		.sector_size = SZ_128K,

		.flags = SPI_NOR_NO_ERASE | SPI_NOR_NO_FR,

		.flags = SPI_NOR_NO_ERASE,

	}, {

		.name = "mr25h40",

		.size = SZ_512K,

		.sector_size = SZ_512K,

		.flags = SPI_NOR_NO_ERASE | SPI_NOR_NO_FR,

		.flags = SPI_NOR_NO_ERASE,

	}

};



static void everspin_nor_default_init(struct spi_nor *nor)

{

	/* Everspin FRAMs don't support the fast read opcode. */

	nor->params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;

}



static const struct spi_nor_fixups everspin_nor_fixups = {

	.default_init = everspin_nor_default_init,

};



const struct spi_nor_manufacturer spi_nor_everspin = {

	.name = "everspin",

	.parts = everspin_nor_parts,

	.nparts = ARRAY_SIZE(everspin_nor_parts),

	.fixups = &everspin_nor_fixups,

};