Commit 2dc8224e authored by Damon Ding's avatar Damon Ding Committed by Vinod Koul
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phy: phy-rockchip-samsung-hdptx: Add the '_MASK' suffix to all registers 



Adding the '_MASK' suffix to all registers in order to ensures consistency
in the naming convention for register macros throughout the file.

Signed-off-by: default avatarDamon Ding <damon.ding@rock-chips.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20250205105157.580060-4-damon.ding@rock-chips.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent f7060241

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

+44 −44
Original line number Diff line number Diff line
@@ -50,60 +50,60 @@ 
#define LCPLL_PI_EN_MASK		BIT(5)

#define LCPLL_100M_CLK_EN_MASK		BIT(0)

/* CMN_REG(0025) */

#define LCPLL_PMS_IQDIV_RSTN		BIT(4)

#define LCPLL_PMS_IQDIV_RSTN_MASK	BIT(4)

/* CMN_REG(0028) */

#define LCPLL_SDC_FRAC_EN		BIT(2)

#define LCPLL_SDC_FRAC_RSTN		BIT(0)

#define LCPLL_SDC_FRAC_EN_MASK		BIT(2)

#define LCPLL_SDC_FRAC_RSTN_MASK	BIT(0)

/* CMN_REG(002d) */

#define LCPLL_SDC_N_MASK		GENMASK(3, 1)

/* CMN_REG(002e) */

#define LCPLL_SDC_NUMBERATOR_MASK	GENMASK(5, 0)

/* CMN_REG(002f) */

#define LCPLL_SDC_DENOMINATOR_MASK	GENMASK(7, 2)

#define LCPLL_SDC_NDIV_RSTN		BIT(0)

#define LCPLL_SDC_NDIV_RSTN_MASK	BIT(0)

/* CMN_REG(003d) */

#define ROPLL_LCVCO_EN			BIT(4)

#define ROPLL_LCVCO_EN_MASK		BIT(4)

/* CMN_REG(004e) */

#define ROPLL_PI_EN			BIT(5)

#define ROPLL_PI_EN_MASK		BIT(5)

/* CMN_REG(005c) */

#define ROPLL_PMS_IQDIV_RSTN		BIT(5)

#define ROPLL_PMS_IQDIV_RSTN_MASK	BIT(5)

/* CMN_REG(005e) */

#define ROPLL_SDM_EN_MASK		BIT(6)

#define ROPLL_SDM_FRAC_EN_RBR		BIT(3)

#define ROPLL_SDM_FRAC_EN_HBR		BIT(2)

#define ROPLL_SDM_FRAC_EN_HBR2		BIT(1)

#define ROPLL_SDM_FRAC_EN_HBR3		BIT(0)

#define ROPLL_SDC_FRAC_EN_RBR_MASK	BIT(3)

#define ROPLL_SDC_FRAC_EN_HBR_MASK	BIT(2)

#define ROPLL_SDC_FRAC_EN_HBR2_MASK	BIT(1)

#define ROPLL_SDM_FRAC_EN_HBR3_MASK	BIT(0)

/* CMN_REG(0064) */

#define ROPLL_SDM_NUM_SIGN_RBR_MASK	BIT(3)

/* CMN_REG(0069) */

#define ROPLL_SDC_N_RBR_MASK		GENMASK(2, 0)

/* CMN_REG(0074) */

#define ROPLL_SDC_NDIV_RSTN		BIT(2)

#define ROPLL_SSC_EN			BIT(0)

#define ROPLL_SDC_NDIV_RSTN_MASK	BIT(2)

#define ROPLL_SSC_EN_MASK		BIT(0)

/* CMN_REG(0081) */

#define OVRD_PLL_CD_CLK_EN		BIT(8)

#define ANA_PLL_CD_HSCLK_EAST_EN	BIT(0)

#define OVRD_PLL_CD_CLK_EN_MASK		BIT(8)

#define ANA_PLL_CD_HSCLK_EAST_EN_MASK	BIT(0)

/* CMN_REG(0086) */

#define PLL_PCG_POSTDIV_SEL_MASK	GENMASK(7, 4)

#define PLL_PCG_CLK_SEL_MASK		GENMASK(3, 1)

#define PLL_PCG_CLK_EN			BIT(0)

#define PLL_PCG_CLK_EN_MASK		BIT(0)

/* CMN_REG(0087) */

#define ANA_PLL_FRL_MODE_EN		BIT(3)

#define ANA_PLL_TX_HS_CLK_EN		BIT(2)

#define ANA_PLL_FRL_MODE_EN_MASK	BIT(3)

#define ANA_PLL_TX_HS_CLK_EN_MASK	BIT(2)

/* CMN_REG(0089) */

#define LCPLL_ALONE_MODE		BIT(1)

#define LCPLL_ALONE_MODE_MASK		BIT(1)

/* CMN_REG(0097) */

#define DIG_CLK_SEL			BIT(1)

#define DIG_CLK_SEL_MASK		BIT(1)

#define LCPLL_REF			BIT(1)

#define ROPLL_REF			0

/* CMN_REG(0099) */

#define CMN_ROPLL_ALONE_MODE		BIT(2)

#define CMN_ROPLL_ALONE_MODE_MASK	BIT(2)

#define ROPLL_ALONE_MODE		BIT(2)

/* CMN_REG(009a) */

#define HS_SPEED_SEL			BIT(0)

#define HS_SPEED_SEL_MASK		BIT(0)

#define DIV_10_CLOCK			BIT(0)

/* CMN_REG(009b) */

#define IS_SPEED_SEL			BIT(4)

#define LS_SPEED_SEL_MASK		BIT(4)

#define LINK_SYMBOL_CLOCK		BIT(4)

#define LINK_SYMBOL_CLOCK1_2		0
@@ -161,36 +161,36 @@ 
#define SB_READY_MASK			BIT(4)



/* LNTOP_REG(0200) */

#define PROTOCOL_SEL			BIT(2)

#define PROTOCOL_SEL_MASK		BIT(2)

#define HDMI_MODE			BIT(2)

#define HDMI_TMDS_FRL_SEL		BIT(1)

/* LNTOP_REG(0206) */

#define DATA_BUS_SEL			BIT(0)

#define DATA_BUS_WIDTH_SEL_MASK		BIT(0)

#define DATA_BUS_36_40			BIT(0)

/* LNTOP_REG(0207) */

#define LANE_EN				0xf

#define LANE_EN_MASK			0xf

#define ALL_LANE_EN			0xf



/* LANE_REG(0312) */

#define LN0_TX_SER_RATE_SEL_RBR		BIT(5)

#define LN0_TX_SER_RATE_SEL_HBR		BIT(4)

#define LN0_TX_SER_RATE_SEL_HBR2	BIT(3)

#define LN0_TX_SER_RATE_SEL_HBR3	BIT(2)

#define LN0_TX_SER_RATE_SEL_RBR_MASK	BIT(5)

#define LN0_TX_SER_RATE_SEL_HBR_MASK	BIT(4)

#define LN0_TX_SER_RATE_SEL_HBR2_MASK	BIT(3)

#define LN0_TX_SER_RATE_SEL_HBR3_MASK	BIT(2)

/* LANE_REG(0412) */

#define LN1_TX_SER_RATE_SEL_RBR		BIT(5)

#define LN1_TX_SER_RATE_SEL_HBR		BIT(4)

#define LN1_TX_SER_RATE_SEL_HBR2	BIT(3)

#define LN1_TX_SER_RATE_SEL_HBR3	BIT(2)

#define LN1_TX_SER_RATE_SEL_RBR_MASK	BIT(5)

#define LN1_TX_SER_RATE_SEL_HBR_MASK	BIT(4)

#define LN1_TX_SER_RATE_SEL_HBR2_MASK	BIT(3)

#define LN1_TX_SER_RATE_SEL_HBR3_MASK	BIT(2)

/* LANE_REG(0512) */

#define LN2_TX_SER_RATE_SEL_RBR		BIT(5)

#define LN2_TX_SER_RATE_SEL_HBR		BIT(4)

#define LN2_TX_SER_RATE_SEL_HBR2	BIT(3)

#define LN2_TX_SER_RATE_SEL_HBR3	BIT(2)

#define LN2_TX_SER_RATE_SEL_RBR_MASK	BIT(5)

#define LN2_TX_SER_RATE_SEL_HBR_MASK	BIT(4)

#define LN2_TX_SER_RATE_SEL_HBR2_MASK	BIT(3)

#define LN2_TX_SER_RATE_SEL_HBR3_MASK	BIT(2)

/* LANE_REG(0612) */

#define LN3_TX_SER_RATE_SEL_RBR		BIT(5)

#define LN3_TX_SER_RATE_SEL_HBR		BIT(4)

#define LN3_TX_SER_RATE_SEL_HBR2	BIT(3)

#define LN3_TX_SER_RATE_SEL_HBR3	BIT(2)

#define LN3_TX_SER_RATE_SEL_RBR_MASK	BIT(5)

#define LN3_TX_SER_RATE_SEL_HBR_MASK	BIT(4)

#define LN3_TX_SER_RATE_SEL_HBR2_MASK	BIT(3)

#define LN3_TX_SER_RATE_SEL_HBR3_MASK	BIT(2)



#define HDMI20_MAX_RATE			600000000
@@ -824,8 +824,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, 
	regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK,

			   FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv));



	regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN,

			   PLL_PCG_CLK_EN);

	regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN_MASK,

			   FIELD_PREP(PLL_PCG_CLK_EN_MASK, 0x1));



	return rk_hdptx_post_enable_pll(hdptx);

}