Commit 2ddf7907 authored by Anup Patel's avatar Anup Patel Committed by Anup Patel
Browse files

KVM: riscv: selftests: Add vector crypto extensions to get-reg-list test 



The KVM RISC-V allows vector crypto extensions for Guest/VM so let us
add these extensions to get-reg-list test. This includes extensions
Zvbb, Zvbc, Zvkb, Zvkg, Zvkned, Zvknha, Zvknhb, Zvksed, Zvksh, and Zvkt.

Signed-off-by: default avatarAnup Patel <apatel@ventanamicro.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent afd1ef3a

tools/testing/selftests/kvm/riscv/get-reg-list.c

+40 −0
Original line number Diff line number Diff line
@@ -69,6 +69,16 @@ bool filter_reg(__u64 reg) 
	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKSED:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKSH:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKT:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBB:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBC:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKB:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKG:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNED:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNHA:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNHB:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKSED:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKSH:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKT:

	/*

	 * Like ISA_EXT registers, SBI_EXT registers are only visible when the

	 * host supports them and disabling them does not affect the visibility
@@ -425,6 +435,16 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) 
		KVM_ISA_EXT_ARR(ZKSED),

		KVM_ISA_EXT_ARR(ZKSH),

		KVM_ISA_EXT_ARR(ZKT),

		KVM_ISA_EXT_ARR(ZVBB),

		KVM_ISA_EXT_ARR(ZVBC),

		KVM_ISA_EXT_ARR(ZVKB),

		KVM_ISA_EXT_ARR(ZVKG),

		KVM_ISA_EXT_ARR(ZVKNED),

		KVM_ISA_EXT_ARR(ZVKNHA),

		KVM_ISA_EXT_ARR(ZVKNHB),

		KVM_ISA_EXT_ARR(ZVKSED),

		KVM_ISA_EXT_ARR(ZVKSH),

		KVM_ISA_EXT_ARR(ZVKT),

	};



	if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name))
@@ -930,6 +950,16 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zkr, ZKR); 
KVM_ISA_EXT_SIMPLE_CONFIG(zksed, ZKSED);

KVM_ISA_EXT_SIMPLE_CONFIG(zksh, ZKSH);

KVM_ISA_EXT_SIMPLE_CONFIG(zkt, ZKT);

KVM_ISA_EXT_SIMPLE_CONFIG(zvbb, ZVBB);

KVM_ISA_EXT_SIMPLE_CONFIG(zvbc, ZVBC);

KVM_ISA_EXT_SIMPLE_CONFIG(zvkb, ZVKB);

KVM_ISA_EXT_SIMPLE_CONFIG(zvkg, ZVKG);

KVM_ISA_EXT_SIMPLE_CONFIG(zvkned, ZVKNED);

KVM_ISA_EXT_SIMPLE_CONFIG(zvknha, ZVKNHA);

KVM_ISA_EXT_SIMPLE_CONFIG(zvknhb, ZVKNHB);

KVM_ISA_EXT_SIMPLE_CONFIG(zvksed, ZVKSED);

KVM_ISA_EXT_SIMPLE_CONFIG(zvksh, ZVKSH);

KVM_ISA_EXT_SIMPLE_CONFIG(zvkt, ZVKT);



struct vcpu_reg_list *vcpu_configs[] = {

	&config_sbi_base,
@@ -967,5 +997,15 @@ struct vcpu_reg_list *vcpu_configs[] = { 
	&config_zksed,

	&config_zksh,

	&config_zkt,

	&config_zvbb,

	&config_zvbc,

	&config_zvkb,

	&config_zvkg,

	&config_zvkned,

	&config_zvknha,

	&config_zvknhb,

	&config_zvksed,

	&config_zvksh,

	&config_zvkt,

};

int vcpu_configs_n = ARRAY_SIZE(vcpu_configs);