Commit 2df50cb4 authored by Vandita Kulkarni's avatar Vandita Kulkarni Committed by Ankit Nautiyal
Browse files

drm/i915/dsc/mtl: Add support for fractional bpp 



Consider the fractional bpp while reading the qp values.

v2: Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)

Signed-off-by: default avatarVandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: default avatarSui Jingfeng <suijingfeng@loongson.cn>
Link: https://patchwork.freedesktop.org/patch/msgid/20231110101020.4067342-6-ankit.k.nautiyal@intel.com
parent 08fcb5ab

drivers/gpu/drm/i915/display/intel_qp_tables.c

+0 −3
Original line number Diff line number Diff line
@@ -34,9 +34,6 @@ 
 * These qp tables are as per the C model

 * and it has the rows pointing to bpps which increment

 * in steps of 0.5

 * We do not support fractional bpps as of today,

 * hence we would skip the fractional bpps during

 * our references for qp calclulations.

 */

static const u8 rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {

	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

drivers/gpu/drm/i915/display/intel_vdsc.c

+20 −5
Original line number Diff line number Diff line
@@ -77,8 +77,8 @@ intel_vdsc_set_min_max_qp(struct drm_dsc_config *vdsc_cfg, int buf, 
static void

calculate_rc_params(struct drm_dsc_config *vdsc_cfg)

{

	int bpp = to_bpp_int(vdsc_cfg->bits_per_pixel);

	int bpc = vdsc_cfg->bits_per_component;

	int bpp = vdsc_cfg->bits_per_pixel >> 4;

	int qp_bpc_modifier = (bpc - 8) * 2;

	int uncompressed_bpg_rate;

	int first_line_bpg_offset;
@@ -148,7 +148,13 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg) 
		static const s8 ofs_und8[] = {

			10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12

		};



		/*

		 * For 420 format since bits_per_pixel (bpp) is set to target bpp * 2,

		 * QP table values for target bpp 4.0 to 4.4375 (rounded to 4.0) are

		 * actually for bpp 8 to 8.875 (rounded to 4.0 * 2 i.e 8).

		 * Similarly values for target bpp 4.5 to 4.8375 (rounded to 4.5)

		 * are for bpp 9 to 9.875 (rounded to 4.5 * 2 i.e 9), and so on.

		 */

		bpp_i  = bpp - 8;

		for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {

			u8 range_bpg_offset;
@@ -178,6 +184,9 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg) 
				range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;

		}

	} else {

		/* fractional bpp part * 10000 (for precision up to 4 decimal places) */

		int fractional_bits = to_bpp_frac(vdsc_cfg->bits_per_pixel);



		static const s8 ofs_und6[] = {

			0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12

		};
@@ -191,7 +200,14 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg) 
			10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12

		};



		bpp_i  = (2 * (bpp - 6));

		/*

		 * QP table rows have values in increment of 0.5.

		 * So 6.0 bpp to 6.4375 will have index 0, 6.5 to 6.9375 will have index 1,

		 * and so on.

		 * 0.5 fractional part with 4 decimal precision becomes 5000

		 */

		bpp_i  = ((bpp - 6) + (fractional_bits < 5000 ? 0 : 1));



		for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {

			u8 range_bpg_offset;
@@ -279,8 +295,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) 
	/* Gen 11 does not support VBR */

	vdsc_cfg->vbr_enable = false;



	/* Gen 11 only supports integral values of bpp */

	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;

	vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp_x16;



	/*

	 * According to DSC 1.2 specs in Section 4.1 if native_420 is set