Commit 2e06b175 authored by Shashank Sharma's avatar Shashank Sharma Committed by Alex Deucher
Browse files

drm/amdgpu: fix userqueue UAPI comments 



This patch fixes some of the pending UAPI review comments
from the libDRM/UAPI review process.

- It updates some outdated comments in the userqueue UAPI header
  highlighted during the libdrm UAPI review.
- It removes the GDS BO support which was found unused.
- It also removes the unused flags parameter from the UAPI.
- It also adds a padding variables in userqueue in/out structures.

(Pierre-Eric and Marek)
  - clarify comments on top of drm_amdgpu_userq_in
  - clarify comment for queue_id (in)
  - clarify comment for mqd
  - clarify comment for compute MQD size
  - clarify comment for queue_id (out)
  - remove GDB object from BO object list
  - remove the unused flags parameter

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarShashank Sharma <shashank.sharma@amd.com>
Signed-off-by: default avatarArvind Yadav <arvind.yadav@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5f2f7831

drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c

+0 −6
Original line number Diff line number Diff line
@@ -225,11 +225,6 @@ amdgpu_userqueue_create(struct drm_file *filp, union drm_amdgpu_userq *args) 
		return -EINVAL;

	}



	if (args->in.flags) {

		DRM_ERROR("Usermode queue flags not supported yet\n");

		return -EINVAL;

	}



	mutex_lock(&uq_mgr->userq_mutex);



	uq_funcs = adev->userq_funcs[args->in.ip_type];
@@ -248,7 +243,6 @@ amdgpu_userqueue_create(struct drm_file *filp, union drm_amdgpu_userq *args) 
	queue->doorbell_handle = args->in.doorbell_handle;

	queue->doorbell_index = args->in.doorbell_offset;

	queue->queue_type = args->in.ip_type;

	queue->flags = args->in.flags;

	queue->vm = &fpriv->vm;



	/* Convert relative doorbell offset into absolute doorbell index */

drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c

+2 −2
Original line number Diff line number Diff line
@@ -201,8 +201,8 @@ static int mes_v11_0_userq_create_ctx_space(struct amdgpu_userq_mgr *uq_mgr, 
		mqd->shadow_base_lo = mqd_gfx_v11->shadow_va & 0xFFFFFFFC;

		mqd->shadow_base_hi = upper_32_bits(mqd_gfx_v11->shadow_va);



		mqd->gds_bkup_base_lo = mqd_gfx_v11->gds_va & 0xFFFFFFFC;

		mqd->gds_bkup_base_hi = upper_32_bits(mqd_gfx_v11->gds_va);

		mqd->gds_bkup_base_lo = 0;

		mqd->gds_bkup_base_hi = 0;



		mqd->fw_work_area_base_lo = mqd_gfx_v11->csa_va & 0xFFFFFFFC;

		mqd->fw_work_area_base_hi = upper_32_bits(mqd_gfx_v11->csa_va);

include/uapi/drm/amdgpu_drm.h

+24 −30
Original line number Diff line number Diff line
@@ -325,35 +325,28 @@ union drm_amdgpu_ctx { 
	union drm_amdgpu_ctx_out out;

};



/* user queue IOCTL */

/* user queue IOCTL operations */

#define AMDGPU_USERQ_OP_CREATE	1

#define AMDGPU_USERQ_OP_FREE	2



/* Flag to indicate secure buffer related workload, unused for now */

#define AMDGPU_USERQ_MQD_FLAGS_SECURE	(1 << 0)

/* Flag to indicate AQL workload, unused for now */

#define AMDGPU_USERQ_MQD_FLAGS_AQL	(1 << 1)



/*

 * MQD (memory queue descriptor) is a set of parameters which allow

 * the GPU to uniquely define and identify a usermode queue. This

 * structure defines the MQD for GFX-V11 IP ver 0.

 * This structure is a container to pass input configuration

 * info for all supported userqueue related operations.

 * For operation AMDGPU_USERQ_OP_CREATE: user is expected

 *  to set all fields, excep the parameter 'queue_id'.

 * For operation AMDGPU_USERQ_OP_FREE: the only input parameter expected

 *  to be set is 'queue_id', eveything else is ignored.

 */

struct drm_amdgpu_userq_in {

	/** AMDGPU_USERQ_OP_* */

	__u32	op;

	/** Queue handle for USERQ_OP_FREE */

	/** Queue id passed for operation USERQ_OP_FREE */

	__u32	queue_id;

	/** the target GPU engine to execute workload (AMDGPU_HW_IP_*) */

	__u32   ip_type;

	/**

	 * @flags: flags to indicate special function for queue like secure

	 * buffer (TMZ). Unused for now.

	 */

	__u32   flags;

	/**

	 * @doorbell_handle: the handle of doorbell GEM object

	 * associated to this client.

	 * associated with this userqueue client.

	 */

	__u32   doorbell_handle;

	/**
@@ -362,7 +355,7 @@ struct drm_amdgpu_userq_in { 
	 * and doorbell_offset in the doorbell bo.

	 */

	__u32   doorbell_offset;



	__u32 _pad;

	/**

	 * @queue_va: Virtual address of the GPU memory which holds the queue

	 * object. The queue holds the workload packets.
@@ -387,25 +380,31 @@ struct drm_amdgpu_userq_in { 
	 */

	__u64   wptr_va;

	/**

	 * @mqd: Queue descriptor for USERQ_OP_CREATE

	 * @mqd: MQD (memory queue descriptor) is a set of parameters which allow

	 * the GPU to uniquely define and identify a usermode queue.

	 *

	 * MQD data can be of different size for different GPU IP/engine and

	 * their respective versions/revisions, so this points to a __u64 *

	 * which holds MQD of this usermode queue.

	 * which holds IP specific MQD of this usermode queue.

	 */

	__u64 mqd;

	/**

	 * @size: size of MQD data in bytes, it must match the MQD structure

	 * size of the respective engine/revision defined in UAPI for ex, for

	 * gfx_v11 workloads, size = sizeof(drm_amdgpu_userq_mqd_gfx_v11).

	 * gfx11 workloads, size = sizeof(drm_amdgpu_userq_mqd_gfx11).

	 */

	__u64 mqd_size;

};



/* The structure to carry output of userqueue ops */

struct drm_amdgpu_userq_out {

	/** Queue handle */

	/**

	 * For operation AMDGPU_USERQ_OP_CREATE: This field contains a unique

	 * queue ID to represent the newly created userqueue in the system, otherwise

	 * it should be ignored.

	 */

	__u32	queue_id;

	/** Flags */

	__u32	flags;

	__u32 _pad;

};



union drm_amdgpu_userq {
@@ -420,11 +419,6 @@ struct drm_amdgpu_userq_mqd_gfx11 { 
	 * Use AMDGPU_INFO_IOCTL to find the exact size of the object.

	 */

	__u64   shadow_va;

	/**

	 * @gds_va: Virtual address of the GPU memory to hold the GDS buffer.

	 * Use AMDGPU_INFO_IOCTL to find the exact size of the object.

	 */

	__u64   gds_va;

	/**

	 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer.

	 * Use AMDGPU_INFO_IOCTL to find the exact size of the object.
@@ -446,8 +440,8 @@ struct drm_amdgpu_userq_mqd_sdma_gfx11 { 
struct drm_amdgpu_userq_mqd_compute_gfx11 {

	/**

	 * @eop_va: Virtual address of the GPU memory to hold the EOP buffer.

	 * This must be a from a separate GPU object, and must be at least 1 page

	 * sized.

	 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL

	 * to get the size.

	 */

	__u64   eop_va;

};