Loading arch/arm/include/asm/mach/map.h +14 −12 Original line number Diff line number Diff line Loading @@ -22,18 +22,20 @@ struct map_desc { }; /* types 0-3 are defined in asm/io.h */ #define MT_UNCACHED 4 #define MT_CACHECLEAN 5 #define MT_MINICLEAN 6 #define MT_LOW_VECTORS 7 #define MT_HIGH_VECTORS 8 #define MT_MEMORY 9 #define MT_ROM 10 #define MT_MEMORY_NONCACHED 11 #define MT_MEMORY_DTCM 12 #define MT_MEMORY_ITCM 13 #define MT_MEMORY_SO 14 #define MT_MEMORY_DMA_READY 15 enum { MT_UNCACHED = 4, MT_CACHECLEAN, MT_MINICLEAN, MT_LOW_VECTORS, MT_HIGH_VECTORS, MT_MEMORY_RWX, MT_ROM, MT_MEMORY_RWX_NONCACHED, MT_MEMORY_RW_DTCM, MT_MEMORY_RWX_ITCM, MT_MEMORY_RW_SO, MT_MEMORY_DMA_READY, }; #ifdef CONFIG_MMU extern void iotable_init(struct map_desc *, int); Loading arch/arm/kernel/tcm.c +2 −2 Original line number Diff line number Diff line Loading @@ -52,7 +52,7 @@ static struct map_desc dtcm_iomap[] __initdata = { .virtual = DTCM_OFFSET, .pfn = __phys_to_pfn(DTCM_OFFSET), .length = 0, .type = MT_MEMORY_DTCM .type = MT_MEMORY_RW_DTCM } }; Loading @@ -61,7 +61,7 @@ static struct map_desc itcm_iomap[] __initdata = { .virtual = ITCM_OFFSET, .pfn = __phys_to_pfn(ITCM_OFFSET), .length = 0, .type = MT_MEMORY_ITCM .type = MT_MEMORY_RWX_ITCM, } }; Loading arch/arm/mach-at91/setup.c +1 −1 Original line number Diff line number Diff line Loading @@ -81,7 +81,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length) desc->pfn = __phys_to_pfn(base); desc->length = length; desc->type = MT_MEMORY_NONCACHED; desc->type = MT_MEMORY_RWX_NONCACHED; pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n", base, length, desc->virtual); Loading arch/arm/mach-omap2/io.c +2 −2 Original line number Diff line number Diff line Loading @@ -244,7 +244,7 @@ static struct map_desc omap44xx_io_desc[] __initdata = { .virtual = OMAP4_SRAM_VA, .pfn = __phys_to_pfn(OMAP4_SRAM_PA), .length = PAGE_SIZE, .type = MT_MEMORY_SO, .type = MT_MEMORY_RW_SO, }, #endif Loading Loading @@ -282,7 +282,7 @@ static struct map_desc omap54xx_io_desc[] __initdata = { .virtual = OMAP4_SRAM_VA, .pfn = __phys_to_pfn(OMAP4_SRAM_PA), .length = PAGE_SIZE, .type = MT_MEMORY_SO, .type = MT_MEMORY_RW_SO, }, #endif }; Loading arch/arm/mach-omap2/omap4-common.c +1 −1 Original line number Diff line number Diff line Loading @@ -88,7 +88,7 @@ void __init omap_barriers_init(void) dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA; dram_io_desc[0].pfn = __phys_to_pfn(paddr); dram_io_desc[0].length = size; dram_io_desc[0].type = MT_MEMORY_SO; dram_io_desc[0].type = MT_MEMORY_RW_SO; iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc)); dram_sync = (void __iomem *) dram_io_desc[0].virtual; sram_sync = (void __iomem *) OMAP4_SRAM_VA; Loading Loading
arch/arm/include/asm/mach/map.h +14 −12 Original line number Diff line number Diff line Loading @@ -22,18 +22,20 @@ struct map_desc { }; /* types 0-3 are defined in asm/io.h */ #define MT_UNCACHED 4 #define MT_CACHECLEAN 5 #define MT_MINICLEAN 6 #define MT_LOW_VECTORS 7 #define MT_HIGH_VECTORS 8 #define MT_MEMORY 9 #define MT_ROM 10 #define MT_MEMORY_NONCACHED 11 #define MT_MEMORY_DTCM 12 #define MT_MEMORY_ITCM 13 #define MT_MEMORY_SO 14 #define MT_MEMORY_DMA_READY 15 enum { MT_UNCACHED = 4, MT_CACHECLEAN, MT_MINICLEAN, MT_LOW_VECTORS, MT_HIGH_VECTORS, MT_MEMORY_RWX, MT_ROM, MT_MEMORY_RWX_NONCACHED, MT_MEMORY_RW_DTCM, MT_MEMORY_RWX_ITCM, MT_MEMORY_RW_SO, MT_MEMORY_DMA_READY, }; #ifdef CONFIG_MMU extern void iotable_init(struct map_desc *, int); Loading
arch/arm/kernel/tcm.c +2 −2 Original line number Diff line number Diff line Loading @@ -52,7 +52,7 @@ static struct map_desc dtcm_iomap[] __initdata = { .virtual = DTCM_OFFSET, .pfn = __phys_to_pfn(DTCM_OFFSET), .length = 0, .type = MT_MEMORY_DTCM .type = MT_MEMORY_RW_DTCM } }; Loading @@ -61,7 +61,7 @@ static struct map_desc itcm_iomap[] __initdata = { .virtual = ITCM_OFFSET, .pfn = __phys_to_pfn(ITCM_OFFSET), .length = 0, .type = MT_MEMORY_ITCM .type = MT_MEMORY_RWX_ITCM, } }; Loading
arch/arm/mach-at91/setup.c +1 −1 Original line number Diff line number Diff line Loading @@ -81,7 +81,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length) desc->pfn = __phys_to_pfn(base); desc->length = length; desc->type = MT_MEMORY_NONCACHED; desc->type = MT_MEMORY_RWX_NONCACHED; pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n", base, length, desc->virtual); Loading
arch/arm/mach-omap2/io.c +2 −2 Original line number Diff line number Diff line Loading @@ -244,7 +244,7 @@ static struct map_desc omap44xx_io_desc[] __initdata = { .virtual = OMAP4_SRAM_VA, .pfn = __phys_to_pfn(OMAP4_SRAM_PA), .length = PAGE_SIZE, .type = MT_MEMORY_SO, .type = MT_MEMORY_RW_SO, }, #endif Loading Loading @@ -282,7 +282,7 @@ static struct map_desc omap54xx_io_desc[] __initdata = { .virtual = OMAP4_SRAM_VA, .pfn = __phys_to_pfn(OMAP4_SRAM_PA), .length = PAGE_SIZE, .type = MT_MEMORY_SO, .type = MT_MEMORY_RW_SO, }, #endif }; Loading
arch/arm/mach-omap2/omap4-common.c +1 −1 Original line number Diff line number Diff line Loading @@ -88,7 +88,7 @@ void __init omap_barriers_init(void) dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA; dram_io_desc[0].pfn = __phys_to_pfn(paddr); dram_io_desc[0].length = size; dram_io_desc[0].type = MT_MEMORY_SO; dram_io_desc[0].type = MT_MEMORY_RW_SO; iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc)); dram_sync = (void __iomem *) dram_io_desc[0].virtual; sram_sync = (void __iomem *) OMAP4_SRAM_VA; Loading