Commit 2e32d580 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2024-06-07' of https://gitlab.freedesktop.org/drm/kernel 

Pull drm fixes from Dave Airlie:
 "Weekly fixes: vmwgfx leads the way this week, with minor changes in xe
  and amdgpu and a couple of other small fixes.

  Seems quiet enough.

  xe:
   - Update the LMTT when freeing VF GT config

  amdgpu:
   - Fix shutdown issues on some SMU 13.x platforms
   - Silence some UBSAN flexible array warnings

  panel:
   - sitronix-st7789v: handle of_drm_get_panel_orientation failing
     error

  vmwgfx:
   - filter modes greater than available graphics memory
   - fix 3D vs STDU enable
   - remove STDU logic from mode valid
   - logging fix
   - memcmp pointers fix
   - remove unused struct
   - screen target lifetime fix

  komeda:
   - unused struct removal"

* tag 'drm-fixes-2024-06-07' of https://gitlab.freedesktop.org/drm/kernel:
  drm/vmwgfx: Don't memcmp equivalent pointers
  drm/vmwgfx: remove unused struct 'vmw_stdu_dma'
  drm/vmwgfx: Don't destroy Screen Target when CRTC is enabled but inactive
  drm/vmwgfx: Standardize use of kibibytes when logging
  drm/vmwgfx: Remove STDU logic from generic mode_valid function
  drm/vmwgfx: 3D disabled should not effect STDU memory limits
  drm/vmwgfx: Filter modes which exceed graphics memory
  drm/amdgpu/pptable: Fix UBSAN array-index-out-of-bounds
  drm/amd: Fix shutdown (again) on some SMU v13.0.4/11 platforms
  drm/xe/pf: Update the LMTT when freeing VF GT config
  drm/panel: sitronix-st7789v: Add check for of_drm_get_panel_orientation
  drm/komeda: remove unused struct 'gamma_curve_segment'
parents 8a929806 eb55943a

drivers/gpu/drm/amd/include/pptable.h

+49 −42
Original line number Diff line number Diff line
@@ -480,7 +480,7 @@ typedef struct _StateArray{ 
	//how many states we have

	UCHAR ucNumEntries;



    ATOM_PPLIB_STATE_V2 states[1];

	ATOM_PPLIB_STATE_V2 states[] /* __counted_by(ucNumEntries) */;

}StateArray;
@@ -495,13 +495,12 @@ typedef struct _ClockInfoArray{ 
}ClockInfoArray;



typedef struct _NonClockInfoArray{



	//how many non-clock levels we have. normally should be same as number of states

	UCHAR ucNumEntries;

	//sizeof(ATOM_PPLIB_NONCLOCK_INFO)

	UCHAR ucEntrySize;



    ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[];

	ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[] __counted_by(ucNumEntries);

}NonClockInfoArray;



typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record
@@ -513,8 +512,10 @@ typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record 


typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table

{

    UCHAR ucNumEntries;                                                // Number of entries.

    ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1];             // Dynamically allocate entries.

	// Number of entries.

	UCHAR ucNumEntries;

	// Dynamically allocate entries.

	ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[] __counted_by(ucNumEntries);

}ATOM_PPLIB_Clock_Voltage_Dependency_Table;



typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record
@@ -529,8 +530,10 @@ typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record 


typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table

{

    UCHAR ucNumEntries;                                                // Number of entries.

    ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1];                  // Dynamically allocate entries.

	// Number of entries.

	UCHAR ucNumEntries;

	// Dynamically allocate entries.

	ATOM_PPLIB_Clock_Voltage_Limit_Record entries[] __counted_by(ucNumEntries);

}ATOM_PPLIB_Clock_Voltage_Limit_Table;



union _ATOM_PPLIB_CAC_Leakage_Record
@@ -553,8 +556,10 @@ typedef union _ATOM_PPLIB_CAC_Leakage_Record ATOM_PPLIB_CAC_Leakage_Record; 


typedef struct _ATOM_PPLIB_CAC_Leakage_Table

{

    UCHAR ucNumEntries;                                                 // Number of entries.

    ATOM_PPLIB_CAC_Leakage_Record entries[1];                           // Dynamically allocate entries.

	// Number of entries.

	UCHAR ucNumEntries;

	// Dynamically allocate entries.

	ATOM_PPLIB_CAC_Leakage_Record entries[] __counted_by(ucNumEntries);

}ATOM_PPLIB_CAC_Leakage_Table;



typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record
@@ -568,8 +573,10 @@ typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record 


typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table

{

    UCHAR ucNumEntries;                                                 // Number of entries.

    ATOM_PPLIB_PhaseSheddingLimits_Record entries[1];                   // Dynamically allocate entries.

	// Number of entries.

	UCHAR ucNumEntries;

	// Dynamically allocate entries.

	ATOM_PPLIB_PhaseSheddingLimits_Record entries[] __counted_by(ucNumEntries);

}ATOM_PPLIB_PhaseSheddingLimits_Table;



typedef struct _VCEClockInfo{
@@ -581,7 +588,7 @@ typedef struct _VCEClockInfo{ 


typedef struct _VCEClockInfoArray{

	UCHAR ucNumEntries;

    VCEClockInfo entries[1];

	VCEClockInfo entries[] __counted_by(ucNumEntries);

}VCEClockInfoArray;



typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record
@@ -593,7 +600,7 @@ typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record 
typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table

{

	UCHAR numEntries;

    ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[1];

	ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[] __counted_by(numEntries);

}ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table;



typedef struct _ATOM_PPLIB_VCE_State_Record
@@ -605,7 +612,7 @@ typedef struct _ATOM_PPLIB_VCE_State_Record 
typedef struct _ATOM_PPLIB_VCE_State_Table

{

	UCHAR numEntries;

    ATOM_PPLIB_VCE_State_Record entries[1];

	ATOM_PPLIB_VCE_State_Record entries[] __counted_by(numEntries);

}ATOM_PPLIB_VCE_State_Table;
@@ -627,7 +634,7 @@ typedef struct _UVDClockInfo{ 


typedef struct _UVDClockInfoArray{

	UCHAR ucNumEntries;

    UVDClockInfo entries[1];

	UVDClockInfo entries[] __counted_by(ucNumEntries);

}UVDClockInfoArray;



typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record
@@ -639,7 +646,7 @@ typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record 
typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table

{

	UCHAR numEntries;

    ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[1];

	ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[] __counted_by(numEntries);

}ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table;



typedef struct _ATOM_PPLIB_UVD_Table
@@ -658,7 +665,7 @@ typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Record 


typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Table{

	UCHAR numEntries;

    ATOM_PPLIB_SAMClk_Voltage_Limit_Record entries[];

	ATOM_PPLIB_SAMClk_Voltage_Limit_Record entries[] __counted_by(numEntries);

}ATOM_PPLIB_SAMClk_Voltage_Limit_Table;



typedef struct _ATOM_PPLIB_SAMU_Table
@@ -676,7 +683,7 @@ typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Record 


typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Table{

	UCHAR numEntries;

    ATOM_PPLIB_ACPClk_Voltage_Limit_Record entries[1];

	ATOM_PPLIB_ACPClk_Voltage_Limit_Record entries[] __counted_by(numEntries);

}ATOM_PPLIB_ACPClk_Voltage_Limit_Table;



typedef struct _ATOM_PPLIB_ACP_Table
@@ -745,7 +752,7 @@ typedef struct ATOM_PPLIB_VQ_Budgeting_Record{ 
typedef struct ATOM_PPLIB_VQ_Budgeting_Table {

	UCHAR revid;

	UCHAR numEntries;

    ATOM_PPLIB_VQ_Budgeting_Record         entries[1];

	ATOM_PPLIB_VQ_Budgeting_Record entries[] __counted_by(numEntries);

} ATOM_PPLIB_VQ_Budgeting_Table;



#pragma pack()

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

+11 −9
Original line number Diff line number Diff line
@@ -226,7 +226,8 @@ static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en) 
	struct amdgpu_device *adev = smu->adev;

	int ret = 0;



	if (!en && adev->in_s4) {

	if (!en && !adev->in_s0ix) {

		if (adev->in_s4) {

			/* Adds a GFX reset as workaround just before sending the

			 * MP1_UNLOAD message to prevent GC/RLC/PMFW from entering

			 * an invalid state.
@@ -235,6 +236,7 @@ static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en) 
							      SMU_RESET_MODE_2, NULL);

			if (ret)

				return ret;

		}



		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);

	}

drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.c

+0 −5
Original line number Diff line number Diff line
@@ -72,11 +72,6 @@ struct gamma_curve_sector { 
	u32 segment_width;

};



struct gamma_curve_segment {

	u32 start;

	u32 end;

};



static struct gamma_curve_sector sector_tbl[] = {

	{ 0,    4,  4   },

	{ 16,   4,  4   },

drivers/gpu/drm/panel/panel-sitronix-st7789v.c

+3 −1
Original line number Diff line number Diff line
@@ -643,7 +643,9 @@ static int st7789v_probe(struct spi_device *spi) 
	if (ret)

		return dev_err_probe(dev, ret, "Failed to get backlight\n");



	of_drm_get_panel_orientation(spi->dev.of_node, &ctx->orientation);

	ret = of_drm_get_panel_orientation(spi->dev.of_node, &ctx->orientation);

	if (ret)

		return dev_err_probe(&spi->dev, ret, "Failed to get orientation\n");



	drm_panel_add(&ctx->panel);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

+6 −13
Original line number Diff line number Diff line
@@ -746,7 +746,7 @@ static int vmw_setup_pci_resources(struct vmw_private *dev, 
		dev->vram_size = pci_resource_len(pdev, 2);



		drm_info(&dev->drm,

			"Register MMIO at 0x%pa size is %llu kiB\n",

			"Register MMIO at 0x%pa size is %llu KiB\n",

			 &rmmio_start, (uint64_t)rmmio_size / 1024);

		dev->rmmio = devm_ioremap(dev->drm.dev,

					  rmmio_start,
@@ -765,7 +765,7 @@ static int vmw_setup_pci_resources(struct vmw_private *dev, 
		fifo_size = pci_resource_len(pdev, 2);



		drm_info(&dev->drm,

			 "FIFO at %pa size is %llu kiB\n",

			 "FIFO at %pa size is %llu KiB\n",

			 &fifo_start, (uint64_t)fifo_size / 1024);

		dev->fifo_mem = devm_memremap(dev->drm.dev,

					      fifo_start,
@@ -790,7 +790,7 @@ static int vmw_setup_pci_resources(struct vmw_private *dev, 
	 * SVGA_REG_VRAM_SIZE.

	 */

	drm_info(&dev->drm,

		 "VRAM at %pa size is %llu kiB\n",

		 "VRAM at %pa size is %llu KiB\n",

		 &dev->vram_start, (uint64_t)dev->vram_size / 1024);



	return 0;
@@ -960,13 +960,6 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id) 
				vmw_read(dev_priv,

					 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);



		/*

		 * Workaround for low memory 2D VMs to compensate for the

		 * allocation taken by fbdev

		 */

		if (!(dev_priv->capabilities & SVGA_CAP_3D))

			mem_size *= 3;



		dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;

		dev_priv->max_primary_mem =

			vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM);
@@ -991,13 +984,13 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id) 
		dev_priv->max_primary_mem = dev_priv->vram_size;

	}

	drm_info(&dev_priv->drm,

		 "Legacy memory limits: VRAM = %llu kB, FIFO = %llu kB, surface = %u kB\n",

		 "Legacy memory limits: VRAM = %llu KiB, FIFO = %llu KiB, surface = %u KiB\n",

		 (u64)dev_priv->vram_size / 1024,

		 (u64)dev_priv->fifo_mem_size / 1024,

		 dev_priv->memory_size / 1024);



	drm_info(&dev_priv->drm,

		 "MOB limits: max mob size = %u kB, max mob pages = %u\n",

		 "MOB limits: max mob size = %u KiB, max mob pages = %u\n",

		 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages);



	ret = vmw_dma_masks(dev_priv);
@@ -1015,7 +1008,7 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id) 
			 (unsigned)dev_priv->max_gmr_pages);

	}

	drm_info(&dev_priv->drm,

		 "Maximum display memory size is %llu kiB\n",

		 "Maximum display memory size is %llu KiB\n",

		 (uint64_t)dev_priv->max_primary_mem / 1024);



	/* Need mmio memory to check for fifo pitchlock cap. */