Unverified Commit 2e706f86 authored by David Lechner's avatar David Lechner Committed by Mark Brown
Browse files

spi: dt-bindings: adi,axi-spi-engine: add multi-lane support 



Extend the ADI AXI SPI engine binding for multiple data lanes. This SPI
controller has a capability to read multiple data words at the same
time (e.g. for use with simultaneous sampling ADCs). The current FPGA
implementation can support up to 8 data lanes at a time (depending on a
compile-time configuration option).

Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Reviewed-by: default avatarJonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: default avatarDavid Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20260123-spi-add-multi-bus-support-v6-6-12af183c06eb@baylibre.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 05c3bd74

Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml

+15 −0
Original line number Diff line number Diff line
@@ -70,6 +70,21 @@ required: 


unevaluatedProperties: false



patternProperties:

  "^.*@[0-9a-f]+":

    type: object



    properties:

      spi-rx-bus-width:

        maxItems: 8

        items:

          enum: [0, 1]



      spi-tx-bus-width:

        maxItems: 8

        items:

          enum: [0, 1]



examples:

  - |

    spi@44a00000 {