Commit 2e9bbdd7 authored by Jiadong Zhu's avatar Jiadong Zhu Committed by Alex Deucher
Browse files

drm/amdgpu/gfx9: implement reset_hw_queue for gfx9 



Using mmio to do queue reset. Enter safe mode
when writing registers.

Acked-by: default avatarVitaly Prosyak <vitaly.prosyak@amd.com>
Signed-off-by: default avatarJiadong Zhu <Jiadong.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 186020c1

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+37 −0
Original line number Diff line number Diff line
@@ -893,6 +893,8 @@ static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, 
static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev);

static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev,

					      unsigned int vmid);

static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);

static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);



static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring,

				uint64_t queue_mask)
@@ -1004,12 +1006,47 @@ static void gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 
			PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));

}





static void gfx_v9_0_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type,

					uint32_t me_id, uint32_t pipe_id, uint32_t queue_id,

					uint32_t xcc_id, uint32_t vmid)

{

	struct amdgpu_device *adev = kiq_ring->adev;

	unsigned i;



	/* enter save mode */

	gfx_v9_0_set_safe_mode(adev, xcc_id);

	mutex_lock(&adev->srbm_mutex);

	soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, 0);



	if (queue_type == AMDGPU_RING_TYPE_COMPUTE) {

		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 0x2);

		WREG32_SOC15(GC, 0, mmSPI_COMPUTE_QUEUE_RESET, 0x1);

		/* wait till dequeue take effects */

		for (i = 0; i < adev->usec_timeout; i++) {

			if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))

				break;

			udelay(1);

		}

		if (i >= adev->usec_timeout)

			dev_err(adev->dev, "fail to wait on hqd deactive\n");

	} else {

		dev_err(adev->dev, "reset queue_type(%d) not supported\n", queue_type);

	}



	soc15_grbm_select(adev, 0, 0, 0, 0, 0);

	mutex_unlock(&adev->srbm_mutex);

	/* exit safe mode */

	gfx_v9_0_unset_safe_mode(adev, xcc_id);

}



static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs = {

	.kiq_set_resources = gfx_v9_0_kiq_set_resources,

	.kiq_map_queues = gfx_v9_0_kiq_map_queues,

	.kiq_unmap_queues = gfx_v9_0_kiq_unmap_queues,

	.kiq_query_status = gfx_v9_0_kiq_query_status,

	.kiq_invalidate_tlbs = gfx_v9_0_kiq_invalidate_tlbs,

	.kiq_reset_hw_queue = gfx_v9_0_kiq_reset_hw_queue,

	.set_resources_size = 8,

	.map_queues_size = 7,

	.unmap_queues_size = 6,