Commit 2ea1f012 authored by Nicolin Chen's avatar Nicolin Chen Committed by Will Deacon
Browse files

iommu/arm-smmu-v3: Pass in cmdq pointer to arm_smmu_cmdq_build_sync_cmd 



The CMDQV extension on NVIDIA Tegra241 SoC only supports CS_NONE in the
CS field of CMD_SYNC, v.s. standard SMMU CMDQ. Pass in the cmdq pointer
directly, so the function can identify a different cmdq implementation.

Reviewed-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Signed-off-by: default avatarNicolin Chen <nicolinc@nvidia.com>
Link: https://lore.kernel.org/r/723288287997b6dfbcd2a904d2c11e9b23f82250.1724970714.git.nicolinc@nvidia.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 56ae8866

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

+6 −4
Original line number Diff line number Diff line
@@ -352,8 +352,9 @@ static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) 
}



static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu,

					 struct arm_smmu_queue *q, u32 prod)

					 struct arm_smmu_cmdq *cmdq, u32 prod)

{

	struct arm_smmu_queue *q = &cmdq->q;

	struct arm_smmu_cmdq_ent ent = {

		.opcode = CMDQ_OP_CMD_SYNC,

	};
@@ -371,7 +372,7 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, 
}



static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu,

				     struct arm_smmu_queue *q)

				     struct arm_smmu_cmdq *cmdq)

{

	static const char * const cerror_str[] = {

		[CMDQ_ERR_CERROR_NONE_IDX]	= "No error",
@@ -379,6 +380,7 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, 
		[CMDQ_ERR_CERROR_ABT_IDX]	= "Abort on command fetch",

		[CMDQ_ERR_CERROR_ATC_INV_IDX]	= "ATC invalidate timeout",

	};

	struct arm_smmu_queue *q = &cmdq->q;



	int i;

	u64 cmd[CMDQ_ENT_DWORDS];
@@ -427,7 +429,7 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, 


static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu)

{

	__arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq.q);

	__arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq);

}



/*
@@ -790,7 +792,7 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, 
	arm_smmu_cmdq_write_entries(cmdq, cmds, llq.prod, n);

	if (sync) {

		prod = queue_inc_prod_n(&llq, n);

		arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, &cmdq->q, prod);

		arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, cmdq, prod);

		queue_write(Q_ENT(&cmdq->q, prod), cmd_sync, CMDQ_ENT_DWORDS);



		/*