Commit 2ef3bb17 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8150: Add DISPCC node 



Years after the SoC support has been added, it's high time for it to
get dispcc going. Add the node to ensure that.

Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # Xperia 5
Reviewed-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229100511.979972-2-konrad.dybcio@linaro.org
parent ac1d8a8e

arch/arm64/boot/dts/qcom/sm8150.dtsi

+23 −0
Original line number Diff line number Diff line
@@ -3594,6 +3594,29 @@ camnoc_virt: interconnect@ac00000 { 
			qcom,bcm-voters = <&apps_bcm_voter>;

		};



		dispcc: clock-controller@af00000 {

			compatible = "qcom,sm8150-dispcc";

			reg = <0 0x0af00000 0 0x10000>;

			clocks = <&rpmhcc RPMH_CXO_CLK>,

				 <0>,

				 <0>,

				 <0>,

				 <0>,

				 <0>,

				 <0>;

			clock-names = "bi_tcxo",

				      "dsi0_phy_pll_out_byteclk",

				      "dsi0_phy_pll_out_dsiclk",

				      "dsi1_phy_pll_out_byteclk",

				      "dsi1_phy_pll_out_dsiclk",

				      "dp_phy_pll_link_clk",

				      "dp_phy_pll_vco_div_clk";

			power-domains = <&rpmhpd SM8150_MMCX>;

			#clock-cells = <1>;

			#reset-cells = <1>;

			#power-domain-cells = <1>;

		};



		pdc: interrupt-controller@b220000 {

			compatible = "qcom,sm8150-pdc", "qcom,pdc";

			reg = <0 0x0b220000 0 0x400>;