Commit 2f22702d authored by Luca Ceresoli's avatar Luca Ceresoli
Browse files

drm/bridge: ti-sn65dsi83: fix CHA_DSI_CLK_RANGE rounding 



The DSI frequency must be in the range:

  (CHA_DSI_CLK_RANGE * 5 MHz) <= DSI freq < ((CHA_DSI_CLK_RANGE + 1) * 5 MHz)

So the register value should point to the lower range value, but
DIV_ROUND_UP() rounds the division to the higher range value, resulting in
an excess of 1 (unless the frequency is an exact multiple of 5 MHz).

For example for a 437100000 MHz clock CHA_DSI_CLK_RANGE should be 87 (0x57):

  (87 * 5 = 435) <= 437.1 < (88 * 5 = 440)

but current code returns 88 (0x58).

Fix the computation by removing the DIV_ROUND_UP().

Fixes: ceb515ba ("drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driver")
Cc: stable@vger.kernel.org
Reviewed-by: default avatarMarek Vasut <marek.vasut@mailbox.org>
Link: https://patch.msgid.link/20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-1-2e15f5a9a6a0@bootlin.com


Signed-off-by: default avatarLuca Ceresoli <luca.ceresoli@bootlin.com>
parent 7149be78

drivers/gpu/drm/bridge/ti-sn65dsi83.c

+3 −3
Original line number Diff line number Diff line
@@ -351,9 +351,9 @@ static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx, 
	 *  DSI_CLK = mode clock * bpp / dsi_data_lanes / 2

	 * the 2 is there because the bus is DDR.

	 */

	return DIV_ROUND_UP(clamp((unsigned int)mode->clock *

	return clamp((unsigned int)mode->clock *

		     mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) /

			    ctx->dsi->lanes / 2, 40000U, 500000U), 5000U);

		     ctx->dsi->lanes / 2, 40000U, 500000U) / 5000U;

}



static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx)