Commit 2f2cc939 authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm: Constify snapshot tables 



A bit of divergence from the downstream driver from which these headers
were imported.  But no need for these tables not to be const.

Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/666656/
parent a506578d

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

+1 −1
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ 
static const unsigned int *gen7_0_0_external_core_regs[] __always_unused;

static const unsigned int *gen7_2_0_external_core_regs[] __always_unused;

static const unsigned int *gen7_9_0_external_core_regs[] __always_unused;

static struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] __always_unused;

static const struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] __always_unused;

static const u32 gen7_9_0_cx_debugbus_blocks[] __always_unused;



#include "adreno_gen7_0_0_snapshot.h"

drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h

+4 −4
Original line number Diff line number Diff line
@@ -81,7 +81,7 @@ static const u32 gen7_0_0_debugbus_blocks[] = { 
	A7XX_DBGBUS_USPTP_7,

};



static struct gen7_shader_block gen7_0_0_shader_blocks[] = {

static const struct gen7_shader_block gen7_0_0_shader_blocks[] = {

	{A7XX_TP0_TMO_DATA,                 0x200, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},

	{A7XX_TP0_SMO_DATA,                  0x80, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},

	{A7XX_TP0_MIPMAP_BASE_DATA,         0x3c0, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
@@ -695,7 +695,7 @@ static const struct gen7_sel_reg gen7_0_0_rb_rbp_sel = { 
	.val = 0x9,

};



static struct gen7_cluster_registers gen7_0_0_clusters[] = {

static const struct gen7_cluster_registers gen7_0_0_clusters[] = {

	{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,

		gen7_0_0_noncontext_pipe_br_registers, },

	{ A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT,
@@ -764,7 +764,7 @@ static struct gen7_cluster_registers gen7_0_0_clusters[] = { 
		gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, },

};



static struct gen7_sptp_cluster_registers gen7_0_0_sptp_clusters[] = {

static const struct gen7_sptp_cluster_registers gen7_0_0_sptp_clusters[] = {

	{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,

		gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers, 0xae00 },

	{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
@@ -914,7 +914,7 @@ static const u32 gen7_0_0_dpm_registers[] = { 
};

static_assert(IS_ALIGNED(sizeof(gen7_0_0_dpm_registers), 8));



static struct gen7_reg_list gen7_0_0_reg_list[] = {

static const struct gen7_reg_list gen7_0_0_reg_list[] = {

	{ gen7_0_0_gpu_registers, NULL },

	{ gen7_0_0_cx_misc_registers, NULL },

	{ gen7_0_0_dpm_registers, NULL },

drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h

+4 −4
Original line number Diff line number Diff line
@@ -95,7 +95,7 @@ static const u32 gen7_2_0_debugbus_blocks[] = { 
	A7XX_DBGBUS_CCHE_2,

};



static struct gen7_shader_block gen7_2_0_shader_blocks[] = {

static const struct gen7_shader_block gen7_2_0_shader_blocks[] = {

	{A7XX_TP0_TMO_DATA,                 0x200, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},

	{A7XX_TP0_SMO_DATA,                  0x80, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},

	{A7XX_TP0_MIPMAP_BASE_DATA,         0x3c0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
@@ -489,7 +489,7 @@ static const struct gen7_sel_reg gen7_2_0_rb_rbp_sel = { 
	.val = 0x9,

};



static struct gen7_cluster_registers gen7_2_0_clusters[] = {

static const struct gen7_cluster_registers gen7_2_0_clusters[] = {

	{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,

		gen7_2_0_noncontext_pipe_br_registers, },

	{ A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT,
@@ -558,7 +558,7 @@ static struct gen7_cluster_registers gen7_2_0_clusters[] = { 
		gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, },

};



static struct gen7_sptp_cluster_registers gen7_2_0_sptp_clusters[] = {

static const struct gen7_sptp_cluster_registers gen7_2_0_sptp_clusters[] = {

	{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,

		gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers, 0xae00 },

	{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
@@ -737,7 +737,7 @@ static const u32 gen7_2_0_dpm_registers[] = { 
};

static_assert(IS_ALIGNED(sizeof(gen7_2_0_dpm_registers), 8));



static struct gen7_reg_list gen7_2_0_reg_list[] = {

static const struct gen7_reg_list gen7_2_0_reg_list[] = {

	{ gen7_2_0_gpu_registers, NULL },

	{ gen7_2_0_cx_misc_registers, NULL },

	{ gen7_2_0_dpm_registers, NULL },

drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h

+5 −5
Original line number Diff line number Diff line
@@ -117,7 +117,7 @@ static const u32 gen7_9_0_cx_debugbus_blocks[] = { 
	A7XX_DBGBUS_GBIF_CX,

};



static struct gen7_shader_block gen7_9_0_shader_blocks[] = {

static const struct gen7_shader_block gen7_9_0_shader_blocks[] = {

	{ A7XX_TP0_TMO_DATA, 0x0200, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },

	{ A7XX_TP0_SMO_DATA, 0x0080, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },

	{ A7XX_TP0_MIPMAP_BASE_DATA, 0x03C0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
@@ -1116,7 +1116,7 @@ static const struct gen7_sel_reg gen7_9_0_rb_rbp_sel = { 
	.val = 0x9,

};



static struct gen7_cluster_registers gen7_9_0_clusters[] = {

static const struct gen7_cluster_registers gen7_9_0_clusters[] = {

	{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,

		gen7_9_0_non_context_pipe_br_registers,  },

	{ A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT,
@@ -1185,7 +1185,7 @@ static struct gen7_cluster_registers gen7_9_0_clusters[] = { 
		gen7_9_0_vpc_pipe_bv_cluster_vpc_ps_registers,  },

};



static struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] = {

static const struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] = {

	{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,

		gen7_9_0_non_context_sp_pipe_br_hlsq_state_registers, 0xae00},

	{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
@@ -1294,7 +1294,7 @@ static struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] = { 
		gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers, 0xb000},

};



static struct a6xx_indexed_registers gen7_9_0_cp_indexed_reg_list[] = {

static const struct a6xx_indexed_registers gen7_9_0_cp_indexed_reg_list[] = {

	{ "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,

		REG_A6XX_CP_SQE_STAT_DATA, 0x00040},

	{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
@@ -1337,7 +1337,7 @@ static struct a6xx_indexed_registers gen7_9_0_cp_indexed_reg_list[] = { 
		REG_A7XX_CP_AQE_STAT_DATA_1, 0x00040},

};



static struct gen7_reg_list gen7_9_0_reg_list[] = {

static const struct gen7_reg_list gen7_9_0_reg_list[] = {

	{ gen7_9_0_gpu_registers, NULL},

	{ gen7_9_0_cx_misc_registers, NULL},

	{ gen7_9_0_cx_dbgc_registers, NULL},