Commit 2f42fb06 authored by Sandipan Das's avatar Sandipan Das Committed by Arnaldo Carvalho de Melo
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perf vendor events amd: Add Zen 6 core events 



Add core events taken from Section 1.5 "Core Performance Monitor
Counters" of the Performance Monitor Counters for AMD Family 1Ah Model
50h-57h Processors document available at the link below.

This constitutes events which capture information on op dispatch,
execution and retirement, branch prediction, L1 and L2 cache activity,
TLB activity, etc.

Reviewed-by: default avatarIan Rogers <irogers@google.com>
Signed-off-by: default avatarSandipan Das <sandipan.das@amd.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ananth Narayan <ananth.narayan@amd.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Stephane Eranian <eranian@google.com>
Link: https://bugzilla.kernel.org/attachment.cgi?id=309149


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 2c3cd43d

tools/perf/pmu-events/arch/x86/amdzen6/branch-prediction.json

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[

  {

    "EventName": "bp_l1_tlb_miss_l2_tlb_hit",

    "EventCode": "0x84",

    "BriefDescription": "Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."

  },

  {

    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if4k",

    "EventCode": "0x85",

    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for 4k pages.",

    "UMask": "0x01"

  },

  {

    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if2m",

    "EventCode": "0x85",

    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for 2M pages.",

    "UMask": "0x02"

  },

  {

    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if1g",

    "EventCode": "0x85",

    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for 1G pages.",

    "UMask": "0x04"

  },

  {

    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k",

    "EventCode": "0x85",

    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for coalesced pages (16k pages created from four adjacent 4k pages).",

    "UMask": "0x08"

  },

  {

    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.all",

    "EventCode": "0x85",

    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for all page sizes.",

    "UMask": "0x0f"

  },

  {

    "EventName": "bp_pipe_correct",

    "EventCode": "0x8b",

    "BriefDescription": "Branch predictor pipeline flushes due to internal conditions such as a second level prediction structure."

  },

  {

    "EventName": "bp_var_target_pred",

    "EventCode": "0x8e",

    "BriefDescription": "Indirect predictions (branch used the indirect predictor to make a prediction)."

  },

  {

    "EventName": "bp_early_redir",

    "EventCode": "0x91",

    "BriefDescription": "Early redirects sent to branch predictor. This happens when either the decoder or dispatch logic is able to detect that the branch predictor needs to be redirected."

  },

  {

    "EventName": "bp_l1_tlb_fetch_hit.if4k",

    "EventCode": "0x94",

    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages (16k pages created from four adjacent 4k pages).",

    "UMask": "0x01"

  },

  {

    "EventName": "bp_l1_tlb_fetch_hit.if2m",

    "EventCode": "0x94",

    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 2M pages.",

    "UMask": "0x02"

  },

  {

    "EventName": "bp_l1_tlb_fetch_hit.if1g",

    "EventCode": "0x94",

    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 1G pages.",

    "UMask": "0x04"

  },

  {

    "EventName": "bp_l1_tlb_fetch_hit.all",

    "EventCode": "0x94",

    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for all page sizes.",

    "UMask": "0x07"

  },

  {

    "EventName": "bp_fe_redir.resync",

    "EventCode": "0x9f",

    "BriefDescription": "Redirects of the pipeline frontend caused by resyncs. These are retire time pipeline restarts.",

    "UMask": "0x01"

  },

  {

    "EventName": "bp_fe_redir.ex_redir",

    "EventCode": "0x9f",

    "BriefDescription": "Redirects of the pipeline frontend caused by mispredicts. These are used for branch direction correction and handling indirect branch target mispredicts.",

    "UMask": "0x02"

  },

  {

    "EventName": "bp_fe_redir.all",

    "EventCode": "0x9f",

    "BriefDescription": "Redirects of the pipeline frontend caused by any reason."

  }

]

tools/perf/pmu-events/arch/x86/amdzen6/decode.json

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[

  {

    "EventName": "de_op_queue_empty",

    "EventCode": "0xa9",

    "BriefDescription": "Cycles where the op queue is empty. Such cycles indicate that the frontend is not delivering instructions fast enough."

  },

  {

    "EventName": "de_src_op_disp.x86_decoder",

    "EventCode": "0xaa",

    "BriefDescription": "Ops dispatched from x86 decoder.",

    "UMask": "0x01"

  },

  {

    "EventName": "de_src_op_disp.op_cache",

    "EventCode": "0xaa",

    "BriefDescription": "Ops dispatched from op cache.",

    "UMask": "0x02"

  },

  {

    "EventName": "de_src_op_disp.all",

    "EventCode": "0xaa",

    "BriefDescription": "Ops dispatched from any source.",

    "UMask": "0x07"

  },

  {

    "EventName": "de_dis_ops_from_decoder.any_fp",

    "EventCode": "0xab",

    "BriefDescription": "Ops dispatched from the decoder to a floating-point unit.",

    "UMask": "0x04"

  },

  {

    "EventName": "de_dis_ops_from_decoder.any_int",

    "EventCode": "0xab",

    "BriefDescription": "Ops dispatched from the decoder to an integer unit.",

    "UMask": "0x08"

  },

  {

    "EventName": "de_disp_stall_cycles_dynamic_tokens_part1.int_phy_reg_file_rsrc_stall",

    "EventCode": "0xae",

    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to integer physical register file resource stalls.",

    "UMask": "0x01"

  },

  {

    "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.load_queue_rsrc_stall",

    "EventCode": "0xae",

    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to load queue token stalls.",

    "UMask": "0x02"

  },

  {

    "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.store_queue_rsrc_stall",

    "EventCode": "0xae",

    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to store queue token stalls.",

    "UMask": "0x04"

  },

  {

    "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.taken_brnch_buffer_rsrc",

    "EventCode": "0xae",

    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to taken branch buffer resource stalls.",

    "UMask": "0x10"

  },

  {

    "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.fp_sch_rsrc_stall",

    "EventCode": "0xae",

    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to floating-point non-schedulable queue token stalls.",

    "UMask": "0x40"

  },

  {

    "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq0",

    "EventCode": "0xaf",

    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 0 tokens.",

    "UMask": "0x01"

  },

  {

    "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq1",

    "EventCode": "0xaf",

    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 1 tokens.",

    "UMask": "0x02"

  },

  {

    "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq2",

    "EventCode": "0xaf",

    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 2 tokens.",

    "UMask": "0x04"

  },

  {

    "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq3",

    "EventCode": "0xaf",

    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 3 tokens.",

    "UMask": "0x08"

  },

  {

    "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq4",

    "EventCode": "0xaf",

    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 4 tokens.",

    "UMask": "0x10"

  },

  {

    "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq5",

    "EventCode": "0xaf",

    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 5 tokens.",

    "UMask": "0x20"

  },

  {

    "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.ret_q",

    "EventCode": "0xaf",

    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of retire queue tokens.",

    "UMask": "0x80"

  },

  {

    "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.all",

    "EventCode": "0xaf",

    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to any token stalls.",

    "UMask": "0xbf"

  },

  {

    "EventName": "de_no_dispatch_per_slot.no_ops_from_frontend",

    "EventCode": "0x1a0",

    "BriefDescription": "Dispatch slots in each cycle that were empty because the frontend did not supply ops.",

    "UMask": "0x01"

  },

  {

    "EventName": "de_no_dispatch_per_slot.backend_stalls",

    "EventCode": "0x1a0",

    "BriefDescription": "Dispatch slots in each cycle that were unused because of backend stalls.",

    "UMask": "0x1e"

  },

  {

    "EventName": "de_no_dispatch_per_slot.smt_contention",

    "EventCode": "0x1a0",

    "BriefDescription": "Dispatch slots in each cycle that were unused because the dispatch cycle was granted to the other SMT thread.",

    "UMask": "0x60"

  },

  {

    "EventName": "de_additional_resource_stalls.dispatch_stalls",

    "EventCode": "0x1a2",

    "BriefDescription": "Counts additional cycles where dispatch is stalled due to a lack of dispatch resources.",

    "UMask": "0x30"

  }

]

tools/perf/pmu-events/arch/x86/amdzen6/execution.json

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[

  {

    "EventName": "ex_ret_instr",

    "EventCode": "0xc0",

    "BriefDescription": "Retired instructions."

  },

  {

    "EventName": "ex_ret_ops",

    "EventCode": "0xc1",

    "BriefDescription": "Retired macro-ops."

  },

  {

    "EventName": "ex_ret_brn",

    "EventCode": "0xc2",

    "BriefDescription": "Retired branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."

  },

  {

    "EventName": "ex_ret_brn_misp",

    "EventCode": "0xc3",

    "BriefDescription": "Retired branch instructions that were mispredicted."

  },

  {

    "EventName": "ex_ret_brn_tkn",

    "EventCode": "0xc4",

    "BriefDescription": "Retired taken branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."

  },

  {

    "EventName": "ex_ret_brn_tkn_misp",

    "EventCode": "0xc5",

    "BriefDescription": "Retired taken branch instructions that were mispredicted."

  },

  {

    "EventName": "ex_ret_brn_far",

    "EventCode": "0xc6",

    "BriefDescription": "Retired far control transfers (far call, far jump, far return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts). Far control transfers are not subject to branch prediction."

  },

  {

    "EventName": "ex_ret_near_ret",

    "EventCode": "0xc8",

    "BriefDescription": "Retired near returns (RET or RET Iw)."

  },

  {

    "EventName": "ex_ret_near_ret_mispred",

    "EventCode": "0xc9",

    "BriefDescription": "Retired near returns that were mispredicted. Each misprediction incurs the same penalty as that of a mispredicted conditional branch instruction."

  },

  {

    "EventName": "ex_ret_brn_ind_misp",

    "EventCode": "0xca",

    "BriefDescription": "Retired indirect branch instructions that were mispredicted (only EX mispredicts). Each misprediction incurs the same penalty as that of a mispredicted conditional branch instruction."

  },

  {

    "EventName": "ex_ret_brn_ind",

    "EventCode": "0xcc",

    "BriefDescription": "Retired indirect branch instructions."

  },

  {

    "EventName": "ex_ret_brn_cond",

    "EventCode": "0xd1",

    "BriefDescription": "Retired conditional branch instructions."

  },

  {

    "EventName": "ex_div_busy",

    "EventCode": "0xd3",

    "BriefDescription": "Cycles where the divider is busy."

  },

  {

    "EventName": "ex_div_count",

    "EventCode": "0xd4",

    "BriefDescription": "Divide ops executed."

  },

  {

    "EventName": "ex_no_retire.empty",

    "EventCode": "0xd6",

    "BriefDescription": "Cycles where the thread does not retire any ops due to a lack of valid ops in the retire queue (may be caused by front-end bottlenecks or pipeline redirects).",

    "UMask": "0x01"

  },

  {

    "EventName": "ex_no_retire.not_complete",

    "EventCode": "0xd6",

    "BriefDescription": "Cycles where the thread does not retire any ops as the oldest retire slot is waiting to be marked as completed.",

    "UMask": "0x02"

  },

  {

    "EventName": "ex_no_retire.other",

    "EventCode": "0xd6",

    "BriefDescription": "Cycles where the thread does not retire any ops due to other reasons (retire breaks, traps, faults, etc.).",

    "UMask": "0x08"

  },

  {

    "EventName": "ex_no_retire.thread_not_selected",

    "EventCode": "0xd6",

    "BriefDescription": "Cycles where the thread does not retire any ops as thread arbitration did not select the current thread.",

    "UMask": "0x10"

  },

  {

    "EventName": "ex_no_retire.load_not_complete",

    "EventCode": "0xd6",

    "BriefDescription": "Cycles where the thread does not retire any ops due to missing load completion.",

    "UMask": "0xa2"

  },

  {

    "EventName": "ex_ret_ucode_instr",

    "EventCode": "0x1c1",

    "BriefDescription": "Retired microcoded instructions."

  },

  {

    "EventName": "ex_ret_ucode_ops",

    "EventCode": "0x1c2",

    "BriefDescription": "Retired microcode ops."

  },

  {

    "EventName": "ex_ret_brn_cond_misp",

    "EventCode": "0x1c7",

    "BriefDescription": "Retired conditional branch instructions that were mispredicted due to direction mismatch."

  },

  {

    "EventName": "ex_ret_brn_uncond_ind_near_misp",

    "EventCode": "0x1c8",

    "BriefDescription": "Retired unconditional indirect near branch instructions that were mispredicted."

  },

  {

    "EventName": "ex_ret_brn_uncond",

    "EventCode": "0x1c9",

    "BriefDescription": "Retired unconditional branch instructions."

  },

  {

    "EventName": "ex_tagged_ibs_ops.tagged",

    "EventCode": "0x1cf",

    "BriefDescription": "Execution IBS tagged ops.",

    "UMask": "0x01"

  },

  {

    "EventName": "ex_tagged_ibs_ops.tagged_ret",

    "EventCode": "0x1cf",

    "BriefDescription": "Execution IBS tagged ops that retired.",

    "UMask": "0x02"

  },

  {

    "EventName": "ex_tagged_ibs_ops.rollovers",

    "EventCode": "0x1cf",

    "BriefDescription": "Execution IBS periodic counter rollovers due to a previous tagged op not being IBS complete.",

    "UMask": "0x04"

  },

  {

    "EventName": "ex_tagged_ibs_ops.filtered",

    "EventCode": "0x1cf",

    "BriefDescription": "Execution IBS tagged ops that retired but were discarded due to IBS filtering.",

    "UMask": "0x08"

  },

  {

    "EventName": "ex_tagged_ibs_ops.valid",

    "EventCode": "0x1cf",

    "BriefDescription": "Execution IBS tagged ops that resulted in a valid sample and an IBS interrupt.",

    "UMask": "0x10"

  },

  {

    "EventName": "ex_ret_fused_instr",

    "EventCode": "0x1d0",

    "BriefDescription": "Retired fused instructions."

  },

  {

    "EventName": "ex_mprof_ibs_ops.tagged",

    "EventCode": "0x2c0",

    "BriefDescription": "Memory Profiler IBS tagged ops.",

    "UMask": "0x01"

  },

  {

    "EventName": "ex_mprof_ibs_ops.tagged_ret",

    "EventCode": "0x2c0",

    "BriefDescription": "Memory Profiler IBS tagged ops that retired.",

    "UMask": "0x02"

  },

  {

    "EventName": "ex_mprof_ibs_ops.rollovers",

    "EventCode": "0x2c0",

    "BriefDescription": "Memory Profiler IBS periodic counter rollovers due to a previous tagged op not being IBS complete.",

    "UMask": "0x04"

  },

  {

    "EventName": "ex_mprof_ibs_ops.filtered",

    "EventCode": "0x2c0",

    "BriefDescription": "Memory Profiler IBS tagged ops that retired but were discarded due to IBS filtering.",

    "UMask": "0x08"

  },

  {

    "EventName": "ex_mprof_ibs_ops.valid",

    "EventCode": "0x2c0",

    "BriefDescription": "Memory Profiler IBS tagged ops that resulted in a valid sample and an IBS interrupt.",

    "UMask": "0x10"

  }

]

tools/perf/pmu-events/arch/x86/amdzen6/floating-point.json

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tools/perf/pmu-events/arch/x86/amdzen6/inst-cache.json

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[

  {

    "EventName": "ic_cache_fill_l2",

    "EventCode": "0x82",

    "BriefDescription": "Instruction cache lines (64 bytes) fulfilled from the L2 cache."

  },

  {

    "EventName": "ic_cache_fill_sys",

    "EventCode": "0x83",

    "BriefDescription": "Instruction cache lines (64 bytes) fulfilled from system memory or another cache."

  },

  {

    "EventName": "ic_fetch_ibs_events.tagged",

    "EventCode": "0x188",

    "BriefDescription": "Fetch IBS tagged fetches. Not all tagged fetches result in a valid sample and an IBS interrupt.",

    "UMask": "0x02"

  },

  {

    "EventName": "ic_fetch_ibs_events.filtered",

    "EventCode": "0x188",

    "BriefDescription": "Fetch IBS tagged fetches that were discarded due to IBS filtering.",

    "UMask": "0x08"

  },

  {

    "EventName": "ic_fetch_ibs_events.valid",

    "EventCode": "0x188",

    "BriefDescription": "Fetch IBS tagged fetches that resulted in a valid sample and an IBS interrupt.",

    "UMask": "0x10"

  },

  {

    "EventName": "op_cache_hit_miss.hit",

    "EventCode": "0x28f",

    "BriefDescription": "Op cache fetch hits.",

    "UMask": "0x03"

  },

  {

    "EventName": "op_cache_hit_miss.miss",

    "EventCode": "0x28f",

    "BriefDescription": "Op cache fetch misses.",

    "UMask": "0x04"

  },

  {

    "EventName": "op_cache_hit_miss.all",

    "EventCode": "0x28f",

    "BriefDescription": "Op cache fetches of all types.",

    "UMask": "0x07"

  },

  {

    "EventName": "ic_fills_from_sys.local_l2",

    "EventCode": "0x29c",

    "BriefDescription": "Instruction cache fills where data is returned from local L2 cache.",

    "UMask": "0x01"

  },

  {

    "EventName": "ic_fills_from_sys.local_ccx",

    "EventCode": "0x29c",

    "BriefDescription": "Instruction cache fills where data is returned from L3 cache or different L2 cache in the same CCX.",

    "UMask": "0x02"

  },

  {

    "EventName": "ic_fills_from_sys.local_all",

    "EventCode": "0x29c",

    "BriefDescription": "Instruction cache fills where data is returned from local L2 cache, L3 cache or different L2 cache in the same CCX.",

    "UMask": "0x03"

  },

  {

    "EventName": "ic_fills_from_sys.near_cache",

    "EventCode": "0x29c",

    "BriefDescription": "Instruction cache fills where data is returned from cache of another CCX in the same NUMA node.",

    "UMask": "0x04"

  },

  {

    "EventName": "ic_fills_from_sys.dram_io_near",

    "EventCode": "0x29c",

    "BriefDescription": "Instruction cache fills where data is returned from either DRAM or MMIO in the same NUMA node.",

    "UMask": "0x08"

  },

  {

    "EventName": "ic_fills_from_sys.far_cache",

    "EventCode": "0x29c",

    "BriefDescription": "Instruction cache fills where data is returned from cache of another CCX in a different NUMA node.",

    "UMask": "0x10"

  },

  {

    "EventName": "ic_fills_from_sys.remote_cache",

    "EventCode": "0x29c",

    "BriefDescription": "Instruction cache fills where data is returned from cache of another CCX in the same or a different NUMA node.",

    "UMask": "0x14"

  },

  {

    "EventName": "ic_fills_from_sys.dram_io_far",

    "EventCode": "0x29c",

    "BriefDescription": "Instruction cache fills where data is returned from either DRAM or MMIO in a different NUMA node.",

    "UMask": "0x40"

  },

  {

    "EventName": "ic_fills_from_sys.dram_io_all",

    "EventCode": "0x29c",

    "BriefDescription": "Instruction cache fills where data is returned from either DRAM or MMIO in the same or a different NUMA node.",

    "UMask": "0x48"

  },

  {

    "EventName": "ic_fills_from_sys.far_all",

    "EventCode": "0x29c",

    "BriefDescription": "Instruction cache fills where data is returned from either cache of another CCX, DRAM or MMIO in a different NUMA node.",

    "UMask": "0x50"

  },

  {

    "EventName": "ic_fills_from_sys.alt_mem",

    "EventCode": "0x29c",

    "BriefDescription": "Instruction cache fills where data is returned from extension memory (CXL).",

    "UMask": "0x80"

  },

  {

    "EventName": "ic_fills_from_sys.all",

    "EventCode": "0x29c",

    "BriefDescription": "Instruction cache fills where data is returned from all types of sources.",

    "UMask": "0xdf"

  }

]