Commit 2f4761c6 authored by Ankit Nautiyal's avatar Ankit Nautiyal
Browse files

drm/i915/dp: Check min bpc DSC limits for dsc_force_bpc also 



For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24.
Check this condition for cases where bpc is forced by debugfs flag
dsc_force_bpc. If the check fails, then WARN and ignore the debugfs
flag.

For MST case the pipe_bpp is already computed (hardcoded to be 24),
and this check is not required.

Signed-off-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230817142459.89764-11-ankit.k.nautiyal@intel.com
parent 8a969033

drivers/gpu/drm/i915/display/intel_dp.c

+31 −17
Original line number Diff line number Diff line
@@ -1694,6 +1694,12 @@ u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915) 
	return HAS_DSC(i915) ? 8 : 0;

}



static

bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)

{

	return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3;

}



int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,

				struct intel_crtc_state *pipe_config,

				struct drm_connector_state *conn_state,
@@ -1705,7 +1711,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 
	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);

	const struct drm_display_mode *adjusted_mode =

		&pipe_config->hw.adjusted_mode;

	int pipe_bpp;

	int ret;



	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
@@ -1717,28 +1722,37 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 
	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))

		return -EINVAL;



	if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {

		pipe_bpp = intel_dp->force_dsc_bpc * 3;

	if (compute_pipe_bpp) {

		int pipe_bpp;

		int forced_bpp = intel_dp->force_dsc_bpc * 3;



		if (forced_bpp && is_dsc_pipe_bpp_sufficient(dev_priv, forced_bpp)) {

			pipe_bpp = forced_bpp;

			drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",

				    intel_dp->force_dsc_bpc);

	} else if (compute_pipe_bpp) {

		pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);

		} else {

		pipe_bpp = pipe_config->pipe_bpp;

	}

			drm_WARN(&dev_priv->drm, forced_bpp,

				 "Cannot force DSC BPC:%d, due to DSC BPC limits\n",

				 intel_dp->force_dsc_bpc);



			pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,

							    conn_state->max_requested_bpc);



	if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) {

			if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {

				drm_dbg_kms(&dev_priv->drm,

					    "Computed BPC less than min supported by source for DSC\n");

				return -EINVAL;

			}

		}



		pipe_config->pipe_bpp = pipe_bpp;

	}



	/*

	 * For now enable DSC for max bpp, max link rate, max lane count.

	 * For now enable DSC for max link rate, max lane count.

	 * Optimize this later for the minimum possible link rate/lane count

	 * with DSC enabled for the requested mode.

	 */

	pipe_config->pipe_bpp = pipe_bpp;

	pipe_config->port_clock = limits->max_rate;

	pipe_config->lane_count = limits->max_lane_count;
@@ -1767,7 +1781,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 
								    adjusted_mode->crtc_hdisplay,

								    pipe_config->bigjoiner_pipes,

								    pipe_config->output_format,

								    pipe_bpp,

								    pipe_config->pipe_bpp,

								    timeslots);

			if (!dsc_max_compressed_bpp) {

				drm_dbg_kms(&dev_priv->drm,