Commit 2f62701f authored by Rob Herring (Arm)'s avatar Rob Herring (Arm) Committed by Will Deacon
Browse files

KVM: arm64: Refine PMU defines for number of counters 



There are 2 defines for the number of PMU counters:
ARMV8_PMU_MAX_COUNTERS and ARMPMU_MAX_HWEVENTS. Both are the same
currently, but Armv9.4/8.9 increases the number of possible counters
from 32 to 33. With this change, the maximum number of counters will
differ for KVM's PMU emulation which is PMUv3.4. Give KVM PMU emulation
its own define to decouple it from the rest of the kernel's number PMU
counters.

The VHE PMU code needs to match the PMU driver, so switch it to use
ARMPMU_MAX_HWEVENTS instead.

Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Reviewed-by: default avatarMarc Zyngier <maz@kernel.org>
Signed-off-by: default avatarRob Herring (Arm) <robh@kernel.org>
Tested-by: default avatarJames Clark <james.clark@linaro.org>
Link: https://lore.kernel.org/r/20240731-arm-pmu-3-9-icntr-v3-6-280a8d7ff465@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 126d7d7c

arch/arm64/kvm/pmu-emul.c

+4 −4
Original line number Diff line number Diff line
@@ -233,7 +233,7 @@ void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu) 
	int i;

	struct kvm_pmu *pmu = &vcpu->arch.pmu;



	for (i = 0; i < ARMV8_PMU_MAX_COUNTERS; i++)

	for (i = 0; i < KVM_ARMV8_PMU_MAX_COUNTERS; i++)

		pmu->pmc[i].idx = i;

}
@@ -260,7 +260,7 @@ void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) 
{

	int i;



	for (i = 0; i < ARMV8_PMU_MAX_COUNTERS; i++)

	for (i = 0; i < KVM_ARMV8_PMU_MAX_COUNTERS; i++)

		kvm_pmu_release_perf_event(kvm_vcpu_idx_to_pmc(vcpu, i));

	irq_work_sync(&vcpu->arch.pmu.overflow_work);

}
@@ -291,7 +291,7 @@ void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val) 
	if (!(kvm_vcpu_read_pmcr(vcpu) & ARMV8_PMU_PMCR_E) || !val)

		return;



	for (i = 0; i < ARMV8_PMU_MAX_COUNTERS; i++) {

	for (i = 0; i < KVM_ARMV8_PMU_MAX_COUNTERS; i++) {

		struct kvm_pmc *pmc;



		if (!(val & BIT(i)))
@@ -323,7 +323,7 @@ void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val) 
	if (!kvm_vcpu_has_pmu(vcpu) || !val)

		return;



	for (i = 0; i < ARMV8_PMU_MAX_COUNTERS; i++) {

	for (i = 0; i < KVM_ARMV8_PMU_MAX_COUNTERS; i++) {

		struct kvm_pmc *pmc;



		if (!(val & BIT(i)))

arch/arm64/kvm/pmu.c

+3 −2
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 
 */

#include <linux/kvm_host.h>

#include <linux/perf_event.h>

#include <linux/perf/arm_pmu.h>

#include <linux/perf/arm_pmuv3.h>



static DEFINE_PER_CPU(struct kvm_pmu_events, kvm_pmu_events);
@@ -95,7 +96,7 @@ static void kvm_vcpu_pmu_enable_el0(unsigned long events) 
	u64 typer;

	u32 counter;



	for_each_set_bit(counter, &events, 32) {

	for_each_set_bit(counter, &events, ARMPMU_MAX_HWEVENTS) {

		typer = kvm_vcpu_pmu_read_evtype_direct(counter);

		typer &= ~ARMV8_PMU_EXCLUDE_EL0;

		kvm_vcpu_pmu_write_evtype_direct(counter, typer);
@@ -110,7 +111,7 @@ static void kvm_vcpu_pmu_disable_el0(unsigned long events) 
	u64 typer;

	u32 counter;



	for_each_set_bit(counter, &events, 32) {

	for_each_set_bit(counter, &events, ARMPMU_MAX_HWEVENTS) {

		typer = kvm_vcpu_pmu_read_evtype_direct(counter);

		typer |= ARMV8_PMU_EXCLUDE_EL0;

		kvm_vcpu_pmu_write_evtype_direct(counter, typer);

include/kvm/arm_pmu.h

+2 −1
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
#include <linux/perf_event.h>

#include <linux/perf/arm_pmuv3.h>



#define KVM_ARMV8_PMU_MAX_COUNTERS	32



#if IS_ENABLED(CONFIG_HW_PERF_EVENTS) && IS_ENABLED(CONFIG_KVM)

struct kvm_pmc {
@@ -25,7 +26,7 @@ struct kvm_pmu_events { 
struct kvm_pmu {

	struct irq_work overflow_work;

	struct kvm_pmu_events events;

	struct kvm_pmc pmc[ARMV8_PMU_MAX_COUNTERS];

	struct kvm_pmc pmc[KVM_ARMV8_PMU_MAX_COUNTERS];

	int irq_num;

	bool created;

	bool irq_level;

include/linux/perf/arm_pmuv3.h

+0 −2
Original line number Diff line number Diff line
@@ -7,8 +7,6 @@ 
#define __PERF_ARM_PMUV3_H



#define ARMV8_PMU_MAX_GENERAL_COUNTERS	31

#define ARMV8_PMU_MAX_COUNTERS	32



#define ARMV8_PMU_CYCLE_IDX		31