Commit 2f7f33a0 authored by Geetha sowjanya's avatar Geetha sowjanya Committed by David S. Miller
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octeontx2-pf: Add representors for sdp MAC 



Hardware supports different types of MACs eg RPM, SDP, LBK.
LBK is for internal Tx->Rx HW loopback path. RPM and SDP MACs support
ingress/egress pkt IO on interfaces with different set of capabilities
like interface modes. At the time of netdev driver registration PF will
seek MAC related information from Admin function driver
'drivers/net/ethernet/marvell/octeontx2/af' and sets up ingress/egress
queues etc such that pkt IO on the channels of these different MACs is
possible. This patch add representors for SDP MAC.

Signed-off-by: default avatarGeetha sowjanya <gakula@marvell.com>
Reviewed-by: default avatarSimon Horman <horms@kernel.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 3392f919

drivers/net/ethernet/marvell/octeontx2/af/common.h

+1 −0
Original line number Diff line number Diff line
@@ -156,6 +156,7 @@ enum nix_scheduler { 
#define	NIC_HW_MIN_FRS			40

#define	NIC_HW_MAX_FRS			9212

#define	SDP_HW_MAX_FRS			65535

#define	SDP_HW_MIN_FRS			16

#define CN10K_LMAC_LINK_MAX_FRS		16380 /* 16k - FCS */

#define CN10K_LBK_LINK_MAX_FRS		65535 /* 64k */

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

+4 −1
Original line number Diff line number Diff line
@@ -586,6 +586,9 @@ int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu, 
	if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK)

		return 0;



	if (is_sdp_pfvf(pcifunc))

		type = NIX_INTF_TYPE_SDP;



	pfvf = rvu_get_pfvf(rvu, pcifunc);

	err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr);

	if (err)
@@ -4687,7 +4690,7 @@ static void nix_link_config(struct rvu *rvu, int blkaddr, 
	if (hw->sdp_links) {

		link = hw->cgx_links + hw->lbk_links;

		rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link),

			    SDP_HW_MAX_FRS << 16 | NIC_HW_MIN_FRS);

			    SDP_HW_MAX_FRS << 16 | SDP_HW_MIN_FRS);

	}



	/* Get MCS external bypass status for CN10K-B */

drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c

+2 −2
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ int cn10k_lmtst_init(struct otx2_nic *pfvf) 
}

EXPORT_SYMBOL(cn10k_lmtst_init);



int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura)

int cn10k_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura)

{

	struct nix_cn10k_aq_enq_req *aq;

	struct otx2_nic *pfvf = dev;
@@ -88,7 +88,7 @@ int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura) 
	aq->sq.ena = 1;

	aq->sq.smq = otx2_get_smq_idx(pfvf, qidx);

	aq->sq.smq_rr_weight = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen);

	aq->sq.default_chan = pfvf->hw.tx_chan_base;

	aq->sq.default_chan = pfvf->hw.tx_chan_base + chan_offset;

	aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */

	aq->sq.sqb_aura = sqb_aura;

	aq->sq.sq_int_ena = NIX_SQINT_BITS;

drivers/net/ethernet/marvell/octeontx2/nic/cn10k.h

+1 −1
Original line number Diff line number Diff line
@@ -26,7 +26,7 @@ static inline int mtu_to_dwrr_weight(struct otx2_nic *pfvf, int mtu) 


int cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);

void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq, int size, int qidx);

int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura);

int cn10k_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura);

int cn10k_lmtst_init(struct otx2_nic *pfvf);

int cn10k_free_all_ipolicers(struct otx2_nic *pfvf);

int cn10k_alloc_matchall_ipolicer(struct otx2_nic *pfvf);

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

+39 −11
Original line number Diff line number Diff line
@@ -253,7 +253,7 @@ int otx2_config_pause_frm(struct otx2_nic *pfvf) 
	struct cgx_pause_frm_cfg *req;

	int err;



	if (is_otx2_lbkvf(pfvf->pdev))

	if (is_otx2_lbkvf(pfvf->pdev) || is_otx2_sdp_rep(pfvf->pdev))

		return 0;



	mutex_lock(&pfvf->mbox.lock);
@@ -647,12 +647,22 @@ int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool txschq_for 
		req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq);

		req->regval[2] =  dwrr_val;

	} else if (lvl == NIX_TXSCH_LVL_TL4) {

		int sdp_chan =  hw->tx_chan_base + prio;



		if (is_otx2_sdp_rep(pfvf->pdev))

			prio = 0;

		parent = schq_list[NIX_TXSCH_LVL_TL3][prio];

		req->reg[0] = NIX_AF_TL4X_PARENT(schq);

		req->regval[0] = (u64)parent << 16;

		req->num_regs++;

		req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq);

		req->regval[1] = dwrr_val;

		if (is_otx2_sdp_rep(pfvf->pdev)) {

			req->num_regs++;

			req->reg[2] = NIX_AF_TL4X_SDP_LINK_CFG(schq);

			req->regval[2] = BIT_ULL(12) | BIT_ULL(13) |

					 (sdp_chan & 0xff);

		}

	} else if (lvl == NIX_TXSCH_LVL_TL3) {

		parent = schq_list[NIX_TXSCH_LVL_TL2][prio];

		req->reg[0] = NIX_AF_TL3X_PARENT(schq);
@@ -660,7 +670,8 @@ int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool txschq_for 
		req->num_regs++;

		req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq);

		req->regval[1] = dwrr_val;

		if (lvl == hw->txschq_link_cfg_lvl) {

		if (lvl == hw->txschq_link_cfg_lvl &&

		    !is_otx2_sdp_rep(pfvf->pdev)) {

			req->num_regs++;

			req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link);

			/* Enable this queue and backpressure
@@ -677,7 +688,8 @@ int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool txschq_for 
		req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq);

		req->regval[1] = (u64)hw->txschq_aggr_lvl_rr_prio << 24 | dwrr_val;



		if (lvl == hw->txschq_link_cfg_lvl) {

		if (lvl == hw->txschq_link_cfg_lvl &&

		    !is_otx2_sdp_rep(pfvf->pdev)) {

			req->num_regs++;

			req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link);

			/* Enable this queue and backpressure
@@ -736,6 +748,7 @@ EXPORT_SYMBOL(otx2_smq_flush); 


int otx2_txsch_alloc(struct otx2_nic *pfvf)

{

	int chan_cnt = pfvf->hw.tx_chan_cnt;

	struct nix_txsch_alloc_req *req;

	struct nix_txsch_alloc_rsp *rsp;

	int lvl, schq, rc;
@@ -748,6 +761,12 @@ int otx2_txsch_alloc(struct otx2_nic *pfvf) 
	/* Request one schq per level */

	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++)

		req->schq[lvl] = 1;



	if (is_otx2_sdp_rep(pfvf->pdev) && chan_cnt > 1) {

		req->schq[NIX_TXSCH_LVL_SMQ] = chan_cnt;

		req->schq[NIX_TXSCH_LVL_TL4] = chan_cnt;

	}



	rc = otx2_sync_mbox_msg(&pfvf->mbox);

	if (rc)

		return rc;
@@ -758,10 +777,12 @@ int otx2_txsch_alloc(struct otx2_nic *pfvf) 
		return PTR_ERR(rsp);



	/* Setup transmit scheduler list */

	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++)

	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {

		pfvf->hw.txschq_cnt[lvl] = rsp->schq[lvl];

		for (schq = 0; schq < rsp->schq[lvl]; schq++)

			pfvf->hw.txschq_list[lvl][schq] =

				rsp->schq_list[lvl][schq];

	}



	pfvf->hw.txschq_link_cfg_lvl = rsp->link_cfg_lvl;

	pfvf->hw.txschq_aggr_lvl_rr_prio = rsp->aggr_lvl_rr_prio;
@@ -799,12 +820,15 @@ EXPORT_SYMBOL(otx2_txschq_free_one); 


void otx2_txschq_stop(struct otx2_nic *pfvf)

{

	int lvl, schq;

	int lvl, schq, idx;



	/* free non QOS TLx nodes */

	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++)

	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {

		for (idx = 0; idx < pfvf->hw.txschq_cnt[lvl]; idx++) {

			otx2_txschq_free_one(pfvf, lvl,

				     pfvf->hw.txschq_list[lvl][0]);

					     pfvf->hw.txschq_list[lvl][idx]);

		}

	}



	/* Clear the txschq list */

	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
@@ -884,7 +908,7 @@ static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura) 
	return otx2_sync_mbox_msg(&pfvf->mbox);

}



int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura)

int otx2_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura)

{

	struct otx2_nic *pfvf = dev;

	struct otx2_snd_queue *sq;
@@ -903,7 +927,7 @@ int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura) 
	aq->sq.ena = 1;

	aq->sq.smq = otx2_get_smq_idx(pfvf, qidx);

	aq->sq.smq_rr_quantum = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen);

	aq->sq.default_chan = pfvf->hw.tx_chan_base;

	aq->sq.default_chan = pfvf->hw.tx_chan_base + chan_offset;

	aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */

	aq->sq.sqb_aura = sqb_aura;

	aq->sq.sq_int_ena = NIX_SQINT_BITS;
@@ -926,6 +950,7 @@ int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) 
	struct otx2_qset *qset = &pfvf->qset;

	struct otx2_snd_queue *sq;

	struct otx2_pool *pool;

	u8 chan_offset;

	int err;



	pool = &pfvf->qset.pool[sqb_aura];
@@ -972,7 +997,8 @@ int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) 
	sq->stats.bytes = 0;

	sq->stats.pkts = 0;



	err = pfvf->hw_ops->sq_aq_init(pfvf, qidx, sqb_aura);

	chan_offset = qidx % pfvf->hw.tx_chan_cnt;

	err = pfvf->hw_ops->sq_aq_init(pfvf, qidx, chan_offset, sqb_aura);

	if (err) {

		kfree(sq->sg);

		sq->sg = NULL;
@@ -1739,6 +1765,8 @@ void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 
	pfvf->hw.sqb_size = rsp->sqb_size;

	pfvf->hw.rx_chan_base = rsp->rx_chan_base;

	pfvf->hw.tx_chan_base = rsp->tx_chan_base;

	pfvf->hw.rx_chan_cnt = rsp->rx_chan_cnt;

	pfvf->hw.tx_chan_cnt = rsp->tx_chan_cnt;

	pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx;

	pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx;

	pfvf->hw.cgx_links = rsp->cgx_links;