Commit 2f8405fb authored by Adam Ford's avatar Adam Ford Committed by Shawn Guo
Browse files

arm64: dts: imx8mp: Fix pgc vpu locations 



The various pgv_vpu nodes have a mismatch between the value after
the @ symbol and what is referenced by 'reg' so reorder the nodes
to align.

Fixes: df680992 ("arm64: dts: imx8mp: add vpu pgc nodes")
Suggested-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: default avatarAdam Ford <aford173@gmail.com>
Reviewd-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 9f05b20c

arch/arm64/boot/dts/freescale/imx8mp.dtsi

+28 −27
Original line number Diff line number Diff line
@@ -838,6 +838,12 @@ pgc_gpumix: power-domain@7 { 
						assigned-clock-rates = <800000000>, <400000000>;

					};



					pgc_vpumix: power-domain@8 {

						#power-domain-cells = <0>;

						reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;

						clocks = <&clk IMX8MP_CLK_VPU_ROOT>;

					};



					pgc_gpu3d: power-domain@9 {

						#power-domain-cells = <0>;

						reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
@@ -853,6 +859,28 @@ pgc_mediamix: power-domain@10 { 
							 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;

					};



					pgc_vpu_g1: power-domain@11 {

						#power-domain-cells = <0>;

						power-domains = <&pgc_vpumix>;

						reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;

						clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;

					};



					pgc_vpu_g2: power-domain@12 {

						#power-domain-cells = <0>;

						power-domains = <&pgc_vpumix>;

						reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;

						clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;



					};



					pgc_vpu_vc8000e: power-domain@13 {

						#power-domain-cells = <0>;

						power-domains = <&pgc_vpumix>;

						reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;

						clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;

					};



					pgc_hdmimix: power-domain@14 {

						#power-domain-cells = <0>;

						reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>;
@@ -890,33 +918,6 @@ pgc_ispdwp: power-domain@18 { 
						reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;

						clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;

					};



					pgc_vpumix: power-domain@19 {

						#power-domain-cells = <0>;

						reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;

						clocks = <&clk IMX8MP_CLK_VPU_ROOT>;

					};



					pgc_vpu_g1: power-domain@20 {

						#power-domain-cells = <0>;

						power-domains = <&pgc_vpumix>;

						reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;

						clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;

					};



					pgc_vpu_g2: power-domain@21 {

						#power-domain-cells = <0>;

						power-domains = <&pgc_vpumix>;

						reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;

						clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;

					};



					pgc_vpu_vc8000e: power-domain@22 {

						#power-domain-cells = <0>;

						power-domains = <&pgc_vpumix>;

						reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;

						clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;

					};

				};

			};

		};