Commit 2f89bb32 authored by Ben Skeggs's avatar Ben Skeggs Committed by Dave Airlie
Browse files

drm/nouveau/pci: add PRI address of config space mirror to nvkm_pci_func 



These registers have moved on GH100/GBxxx, and the GSP-RM init code uses
hardcoded values from earlier GPUs to fill GspSystemInfo.

Replace the per-GPU accessors in nvkm_pci_func with region info, and use
it when initialising GspSystemInfo.

Signed-off-by: default avatarBen Skeggs <bskeggs@nvidia.com>
Reviewed-by: default avatarDave Airlie <airlied@redhat.com>
Reviewed-by: default avatarTimur Tabi <ttabi@nvidia.com>
Tested-by: default avatarTimur Tabi <ttabi@nvidia.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 53dac062

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

+3 −2
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
#include "priv.h"



#include <core/pci.h>

#include <subdev/pci/priv.h>

#include <subdev/timer.h>

#include <subdev/vfn.h>

#include <engine/fifo/chan.h>
@@ -905,8 +906,8 @@ r535_gsp_set_system_info(struct nvkm_gsp *gsp) 
	info->gpuPhysInstAddr = device->func->resource_addr(device, 3);

	info->nvDomainBusDeviceFunc = pci_dev_id(pdev->pdev);

	info->maxUserVa = TASK_SIZE;

	info->pciConfigMirrorBase = 0x088000;

	info->pciConfigMirrorSize = 0x001000;

	info->pciConfigMirrorBase = device->pci->func->cfg.addr;

	info->pciConfigMirrorSize = device->pci->func->cfg.size;

	r535_gsp_acpi_info(gsp, &info->acpiMethodData);



	return nvkm_gsp_rpc_wr(gsp, info, NVKM_GSP_RPC_REPLY_NOWAIT);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gsp.c

+3 −2
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include "nvrm/msgfn.h"



#include <core/pci.h>

#include <subdev/pci/priv.h>



static u32

r570_gsp_sr_data_size(struct nvkm_gsp *gsp)
@@ -157,8 +158,8 @@ r570_gsp_set_system_info(struct nvkm_gsp *gsp) 
	info->gpuPhysInstAddr = device->func->resource_addr(device, 3);

	info->nvDomainBusDeviceFunc = pci_dev_id(pdev);

	info->maxUserVa = TASK_SIZE;

	info->pciConfigMirrorBase = 0x088000;

	info->pciConfigMirrorSize = 0x001000;

	info->pciConfigMirrorBase = device->pci->func->cfg.addr;

	info->pciConfigMirrorSize = device->pci->func->cfg.size;

	info->PCIDeviceID = (pdev->device << 16) | pdev->vendor;

	info->PCISubDeviceID = (pdev->subsystem_device << 16) | pdev->subsystem_vendor;

	info->PCIRevisionID = pdev->revision;

drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c

+5 −5
Original line number Diff line number Diff line
@@ -39,26 +39,26 @@ nvkm_pci_msi_rearm(struct nvkm_device *device) 
u32

nvkm_pci_rd32(struct nvkm_pci *pci, u16 addr)

{

	return pci->func->rd32(pci, addr);

	return nvkm_rd32(pci->subdev.device, pci->func->cfg.addr + addr);

}



void

nvkm_pci_wr08(struct nvkm_pci *pci, u16 addr, u8 data)

{

	pci->func->wr08(pci, addr, data);

	nvkm_wr08(pci->subdev.device, pci->func->cfg.addr + addr, data);

}



void

nvkm_pci_wr32(struct nvkm_pci *pci, u16 addr, u32 data)

{

	pci->func->wr32(pci, addr, data);

	nvkm_wr32(pci->subdev.device, pci->func->cfg.addr + addr, data);

}



u32

nvkm_pci_mask(struct nvkm_pci *pci, u16 addr, u32 mask, u32 value)

{

	u32 data = pci->func->rd32(pci, addr);

	pci->func->wr32(pci, addr, (data & ~mask) | value);

	u32 data = nvkm_pci_rd32(pci, addr);

	nvkm_pci_wr32(pci, addr, (data & ~mask) | value);

	return data;

}

drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c

+2 −3
Original line number Diff line number Diff line
@@ -132,10 +132,9 @@ g84_pcie_init(struct nvkm_pci *pci) 


static const struct nvkm_pci_func

g84_pci_func = {

	.cfg = { .addr = 0x088000, .size = 0x1000 },



	.init = g84_pci_init,

	.rd32 = nv40_pci_rd32,

	.wr08 = nv40_pci_wr08,

	.wr32 = nv40_pci_wr32,

	.msi_rearm = nv46_pci_msi_rearm,



	.pcie.init = g84_pcie_init,

drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c

+2 −3
Original line number Diff line number Diff line
@@ -33,10 +33,9 @@ g92_pcie_version_supported(struct nvkm_pci *pci) 


static const struct nvkm_pci_func

g92_pci_func = {

	.cfg = { .addr = 0x088000, .size = 0x1000 },



	.init = g84_pci_init,

	.rd32 = nv40_pci_rd32,

	.wr08 = nv40_pci_wr08,

	.wr32 = nv40_pci_wr32,

	.msi_rearm = nv46_pci_msi_rearm,



	.pcie.init = g84_pcie_init,