Commit 2fddca72 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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arm64: dts: renesas: Add initial DTS for RZ/V2H EVK board 



Add initial DTS for RZ/V2H EVK board (based on R9A09G057H44), adding
the below support:
- Memory
- Clock inputs
- PINCTRL
- SCIF

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240828124134.188864-4-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 740cf2a2

arch/arm64/boot/dts/renesas/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -140,5 +140,7 @@ dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb 


dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb



dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk.dtb



dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo

dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo

arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts

0 → 100644
+61 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

/*

 * Device Tree Source for the RZ/V2H EVK board

 *

 * Copyright (C) 2024 Renesas Electronics Corp.

 */



/dts-v1/;



#include "r9a09g057.dtsi"



/ {

	model = "Renesas RZ/V2H EVK Board based on r9a09g057h44";

	compatible = "renesas,rzv2h-evk", "renesas,r9a09g057h44", "renesas,r9a09g057";



	aliases {

		serial0 = &scif;

	};



	chosen {

		bootargs = "ignore_loglevel";

		stdout-path = "serial0:115200n8";

	};



	memory@48000000 {

		device_type = "memory";

		/* first 128MB is reserved for secure area. */

		reg = <0x0 0x48000000 0x1 0xF8000000>;

	};



	memory@240000000 {

		device_type = "memory";

		reg = <0x2 0x40000000 0x2 0x00000000>;

	};

};



&audio_extal_clk {

	clock-frequency = <22579200>;

};



&pinctrl {

	scif_pins: scif {

		pins = "SCIF_TXD", "SCIF_RXD";

		renesas,output-impedance = <1>;

	};

};



&qextal_clk {

	clock-frequency = <24000000>;

};



&rtxin_clk {

	clock-frequency = <32768>;

};



&scif {

	pinctrl-0 = <&scif_pins>;

	pinctrl-names = "default";



	status = "okay";

};