Commit 3006f7fb authored by Abel Vesa's avatar Abel Vesa Committed by Bjorn Andersson
Browse files

clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock 



According to internal documentation, the UFS AXI PHY clock requires
FORCE_MEM_CORE_ON to be enabled for UFS MCQ mode to work. Without this,
the UFS controller fails when operating in MCQ mode, which is already
enabled in the device tree.

The UFS PHY ICE core clock already has this bit set, so apply the same
configuration to the UFS PHY AXI clock.

Fixes: 3d356ab4 ("clk: qcom: Add support for Global clock controller on Eliza")
Reported-by: default avatarNitin Rawat <nitin.rawat@oss.qualcomm.com>
Signed-off-by: default avatarAbel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: default avatarTaniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260323-eliza-gcc-set-ufs-axi-phyforce-mem-core-on-v1-1-b6b7a6f3f8c5@oss.qualcomm.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent b0bc6011

drivers/clk/qcom/gcc-eliza.c

+2 −1
Original line number Diff line number Diff line
@@ -3046,8 +3046,9 @@ static const struct regmap_config gcc_eliza_regmap_config = { 


static void clk_eliza_regs_configure(struct device *dev, struct regmap *regmap)

{

	/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */

	/* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks  */

	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);

	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);

}



static struct qcom_cc_driver_data gcc_eliza_driver_data = {