Commit 30176bf7 authored by Ivan Vecera's avatar Ivan Vecera Committed by Jakub Kicinski
Browse files

dpll: add phase-adjust-gran pin attribute 



Phase-adjust values are currently limited by a min-max range. Some
hardware requires, for certain pin types, that values be multiples of
a specific granularity, as in the zl3073x driver.

Add a `phase-adjust-gran` pin attribute and an appropriate field in
dpll_pin_properties. If set by the driver, use its value to validate
user-provided phase-adjust values.

Reviewed-by: default avatarMichal Schmidt <mschmidt@redhat.com>
Reviewed-by: default avatarPetr Oros <poros@redhat.com>
Tested-by: default avatarPrathosh Satish <Prathosh.Satish@microchip.com>
Signed-off-by: default avatarIvan Vecera <ivecera@redhat.com>
Reviewed-by: default avatarJiri Pirko <jiri@nvidia.com>
Reviewed-by: default avatarArkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Link: https://patch.msgid.link/20251029153207.178448-2-ivecera@redhat.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 29f7ae9e

Documentation/driver-api/dpll.rst

+20 −16
Original line number Diff line number Diff line
@@ -198,15 +198,17 @@ be requested with the same attribute with ``DPLL_CMD_DEVICE_SET`` command. 
  ================================== ======================================



Device may also provide ability to adjust a signal phase on a pin.

If pin phase adjustment is supported, minimal and maximal values that pin

handle shall be provide to the user on ``DPLL_CMD_PIN_GET`` respond

with ``DPLL_A_PIN_PHASE_ADJUST_MIN`` and ``DPLL_A_PIN_PHASE_ADJUST_MAX``

If pin phase adjustment is supported, minimal and maximal values and

granularity that pin handle shall be provided to the user on

``DPLL_CMD_PIN_GET`` respond with ``DPLL_A_PIN_PHASE_ADJUST_MIN``,

``DPLL_A_PIN_PHASE_ADJUST_MAX`` and ``DPLL_A_PIN_PHASE_ADJUST_GRAN``

attributes. Configured phase adjust value is provided with

``DPLL_A_PIN_PHASE_ADJUST`` attribute of a pin, and value change can be

requested with the same attribute with ``DPLL_CMD_PIN_SET`` command.



  =============================== ======================================

  ================================ ==========================================

  ``DPLL_A_PIN_ID``                configured pin id

  ``DPLL_A_PIN_PHASE_ADJUST_GRAN`` attr granularity of phase adjustment value

  ``DPLL_A_PIN_PHASE_ADJUST_MIN``  attr minimum value of phase adjustment

  ``DPLL_A_PIN_PHASE_ADJUST_MAX``  attr maximum value of phase adjustment

  ``DPLL_A_PIN_PHASE_ADJUST``      attr configured value of phase
@@ -217,7 +219,7 @@ requested with the same attribute with ``DPLL_CMD_PIN_SET`` command. 
    ``DPLL_A_PIN_PARENT_ID``       parent dpll device id

    ``DPLL_A_PIN_PHASE_OFFSET``    attr measured phase difference

                                   between a pin and parent dpll device

  =============================== ======================================

  ================================ ==========================================



All phase related values are provided in pico seconds, which represents

time difference between signals phase. The negative value means that
@@ -384,6 +386,8 @@ according to attribute purpose. 
                                       frequencies

      ``DPLL_A_PIN_ANY_FREQUENCY_MIN`` attr minimum value of frequency

      ``DPLL_A_PIN_ANY_FREQUENCY_MAX`` attr maximum value of frequency

    ``DPLL_A_PIN_PHASE_ADJUST_GRAN``   attr granularity of phase

                                       adjustment value

    ``DPLL_A_PIN_PHASE_ADJUST_MIN``    attr minimum value of phase

                                       adjustment

    ``DPLL_A_PIN_PHASE_ADJUST_MAX``    attr maximum value of phase

Documentation/netlink/specs/dpll.yaml

+7 −0
Original line number Diff line number Diff line
@@ -440,6 +440,12 @@ attribute-sets: 
        doc: |

          Capable pin provides list of pins that can be bound to create a

          reference-sync pin pair.

      -

        name: phase-adjust-gran

        type: u32

        doc: |

          Granularity of phase adjustment, in picoseconds. The value of

          phase adjustment must be a multiple of this granularity.



  -

    name: pin-parent-device
@@ -616,6 +622,7 @@ operations: 
            - capabilities

            - parent-device

            - parent-pin

            - phase-adjust-gran

            - phase-adjust-min

            - phase-adjust-max

            - phase-adjust

drivers/dpll/dpll_netlink.c

+11 −1
Original line number Diff line number Diff line
@@ -637,6 +637,10 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin, 
	ret = dpll_msg_add_pin_freq(msg, pin, ref, extack);

	if (ret)

		return ret;

	if (prop->phase_gran &&

	    nla_put_u32(msg, DPLL_A_PIN_PHASE_ADJUST_GRAN,

			prop->phase_gran))

		return -EMSGSIZE;

	if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN,

			prop->phase_range.min))

		return -EMSGSIZE;
@@ -1261,7 +1265,13 @@ dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr *phase_adj_attr, 
	if (phase_adj > pin->prop.phase_range.max ||

	    phase_adj < pin->prop.phase_range.min) {

		NL_SET_ERR_MSG_ATTR(extack, phase_adj_attr,

				    "phase adjust value not supported");

				    "phase adjust value of out range");

		return -EINVAL;

	}

	if (pin->prop.phase_gran && phase_adj % (s32)pin->prop.phase_gran) {

		NL_SET_ERR_MSG_ATTR_FMT(extack, phase_adj_attr,

					"phase adjust value not multiple of %u",

					pin->prop.phase_gran);

		return -EINVAL;

	}

include/linux/dpll.h

+1 −0
Original line number Diff line number Diff line
@@ -163,6 +163,7 @@ struct dpll_pin_properties { 
	u32 freq_supported_num;

	struct dpll_pin_frequency *freq_supported;

	struct dpll_pin_phase_adjust_range phase_range;

	u32 phase_gran;

};



#if IS_ENABLED(CONFIG_DPLL)

include/uapi/linux/dpll.h

+1 −0
Original line number Diff line number Diff line
@@ -251,6 +251,7 @@ enum dpll_a_pin { 
	DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED,

	DPLL_A_PIN_ESYNC_PULSE,

	DPLL_A_PIN_REFERENCE_SYNC,

	DPLL_A_PIN_PHASE_ADJUST_GRAN,



	__DPLL_A_PIN_MAX,

	DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)