Commit 3022bf37 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'gpio-fixes-for-v6.9-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux 

Pull gpio fixes from Bartosz Golaszewski:

 - fix a regression in pin access control in gpio-tegra186

 - make data pointer dereference robust in Intel Tangier driver

* tag 'gpio-fixes-for-v6.9-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux:
  gpio: tegra186: Fix tegra186_gpio_is_accessible() check
  gpio: tangier: Use correct type for the IRQ chip data
parents 5b43efa1 c714fcdf

drivers/gpio/gpio-tangier.c

+6 −3
Original line number Diff line number Diff line
@@ -195,7 +195,8 @@ static int tng_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 


static void tng_irq_ack(struct irq_data *d)

{

	struct tng_gpio *priv = irq_data_get_irq_chip_data(d);

	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);

	struct tng_gpio *priv = gpiochip_get_data(gc);

	irq_hw_number_t gpio = irqd_to_hwirq(d);

	void __iomem *gisr;

	u8 shift;
@@ -227,7 +228,8 @@ static void tng_irq_unmask_mask(struct tng_gpio *priv, u32 gpio, bool unmask) 


static void tng_irq_mask(struct irq_data *d)

{

	struct tng_gpio *priv = irq_data_get_irq_chip_data(d);

	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);

	struct tng_gpio *priv = gpiochip_get_data(gc);

	irq_hw_number_t gpio = irqd_to_hwirq(d);



	tng_irq_unmask_mask(priv, gpio, false);
@@ -236,7 +238,8 @@ static void tng_irq_mask(struct irq_data *d) 


static void tng_irq_unmask(struct irq_data *d)

{

	struct tng_gpio *priv = irq_data_get_irq_chip_data(d);

	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);

	struct tng_gpio *priv = gpiochip_get_data(gc);

	irq_hw_number_t gpio = irqd_to_hwirq(d);



	gpiochip_enable_irq(&priv->chip, gpio);

drivers/gpio/gpio-tegra186.c

+11 −9
Original line number Diff line number Diff line
@@ -36,12 +36,6 @@ 
#define  TEGRA186_GPIO_SCR_SEC_REN		BIT(27)

#define  TEGRA186_GPIO_SCR_SEC_G1W		BIT(9)

#define  TEGRA186_GPIO_SCR_SEC_G1R		BIT(1)

#define  TEGRA186_GPIO_FULL_ACCESS		(TEGRA186_GPIO_SCR_SEC_WEN | \

						 TEGRA186_GPIO_SCR_SEC_REN | \

						 TEGRA186_GPIO_SCR_SEC_G1R | \

						 TEGRA186_GPIO_SCR_SEC_G1W)

#define  TEGRA186_GPIO_SCR_SEC_ENABLE		(TEGRA186_GPIO_SCR_SEC_WEN | \

						 TEGRA186_GPIO_SCR_SEC_REN)



/* control registers */

#define TEGRA186_GPIO_ENABLE_CONFIG 0x00
@@ -177,10 +171,18 @@ static inline bool tegra186_gpio_is_accessible(struct tegra_gpio *gpio, unsigned 


	value = __raw_readl(secure + TEGRA186_GPIO_SCR);



	if ((value & TEGRA186_GPIO_SCR_SEC_ENABLE) == 0)

		return true;

	/*

	 * When SCR_SEC_[R|W]EN is unset, then we have full read/write access to all the

	 * registers for given GPIO pin.

	 * When SCR_SEC[R|W]EN is set, then there is need to further check the accompanying

	 * SCR_SEC_G1[R|W] bit to determine read/write access to all the registers for given

	 * GPIO pin.

	 */



	if ((value & TEGRA186_GPIO_FULL_ACCESS) == TEGRA186_GPIO_FULL_ACCESS)

	if (((value & TEGRA186_GPIO_SCR_SEC_REN) == 0 ||

	     ((value & TEGRA186_GPIO_SCR_SEC_REN) && (value & TEGRA186_GPIO_SCR_SEC_G1R))) &&

	     ((value & TEGRA186_GPIO_SCR_SEC_WEN) == 0 ||

	     ((value & TEGRA186_GPIO_SCR_SEC_WEN) && (value & TEGRA186_GPIO_SCR_SEC_G1W))))

		return true;



	return false;