Commit 3034cc81 authored by Matt Roper's avatar Matt Roper
Browse files

drm/xe/pcode: Treat pcode as per-tile rather than per-GT 



There's only one instance of the pcode per tile, and for GT-related
accesses both the primary and media GT share the same register
interface.  Since Xe was using per-GT locking, the pcode mutex wasn't
actually protecting everything that it should since concurrent accesses
related to a tile's primary GT and media GT were possible.

Fixes: dd08ebf6 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240829220619.789159-5-matthew.d.roper@intel.com
parent cad08fa7

drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h

+4 −4
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ static inline int 
snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,

			int fast_timeout_us, int slow_timeout_ms)

{

	return xe_pcode_write_timeout(__compat_uncore_to_gt(uncore), mbox, val,

	return xe_pcode_write_timeout(__compat_uncore_to_tile(uncore), mbox, val,

				      slow_timeout_ms ?: 1);

}
@@ -21,13 +21,13 @@ static inline int 
snb_pcode_write(struct intel_uncore *uncore, u32 mbox, u32 val)

{



	return xe_pcode_write(__compat_uncore_to_gt(uncore), mbox, val);

	return xe_pcode_write(__compat_uncore_to_tile(uncore), mbox, val);

}



static inline int

snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1)

{

	return xe_pcode_read(__compat_uncore_to_gt(uncore), mbox, val, val1);

	return xe_pcode_read(__compat_uncore_to_tile(uncore), mbox, val, val1);

}



static inline int
@@ -35,7 +35,7 @@ skl_pcode_request(struct intel_uncore *uncore, u32 mbox, 
		  u32 request, u32 reply_mask, u32 reply,

		  int timeout_base_ms)

{

	return xe_pcode_request(__compat_uncore_to_gt(uncore), mbox, request, reply_mask, reply,

	return xe_pcode_request(__compat_uncore_to_tile(uncore), mbox, request, reply_mask, reply,

				timeout_base_ms);

}

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

+7 −0
Original line number Diff line number Diff line
@@ -17,6 +17,13 @@ static inline struct xe_gt *__compat_uncore_to_gt(struct intel_uncore *uncore) 
	return xe_root_mmio_gt(xe);

}



static inline struct xe_tile *__compat_uncore_to_tile(struct intel_uncore *uncore)

{

	struct xe_device *xe = container_of(uncore, struct xe_device, uncore);



	return xe_device_get_root_tile(xe);

}



static inline u32 intel_uncore_read(struct intel_uncore *uncore,

				    i915_reg_t i915_reg)

{

drivers/gpu/drm/xe/xe_device_types.h

+6 −0
Original line number Diff line number Diff line
@@ -208,6 +208,12 @@ struct xe_tile { 
		} vf;

	} sriov;



	/** @pcode: tile's PCODE */

	struct {

		/** @pcode.lock: protecting tile's PCODE mailbox data */

		struct mutex lock;

	} pcode;



	/** @migrate: Migration helper for vram blits and clearing */

	struct xe_migrate *migrate;

drivers/gpu/drm/xe/xe_gt.c

+0 −2
Original line number Diff line number Diff line
@@ -46,7 +46,6 @@ 
#include "xe_migrate.h"

#include "xe_mmio.h"

#include "xe_pat.h"

#include "xe_pcode.h"

#include "xe_pm.h"

#include "xe_mocs.h"

#include "xe_reg_sr.h"
@@ -386,7 +385,6 @@ int xe_gt_init_early(struct xe_gt *gt) 
	xe_tuning_process_gt(gt);



	xe_force_wake_init_gt(gt, gt_to_fw(gt));

	xe_pcode_init(gt);

	spin_lock_init(&gt->global_invl_lock);



	return 0;

drivers/gpu/drm/xe/xe_gt_types.h

+0 −6
Original line number Diff line number Diff line
@@ -329,12 +329,6 @@ struct xe_gt { 
	/** @eclass: per hardware engine class interface on the GT */

	struct xe_hw_engine_class_intf  eclass[XE_ENGINE_CLASS_MAX];



	/** @pcode: GT's PCODE */

	struct {

		/** @pcode.lock: protecting GT's PCODE mailbox data */

		struct mutex lock;

	} pcode;



	/** @sysfs: sysfs' kobj used by xe_gt_sysfs */

	struct kobject *sysfs;