Commit 305448e5 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Query the vswing levels per-lane for icl mg phy 



Prepare for per-lane drive settings by querying the desired vswing
level per-lane.

Note that the code only does two loops, with each one writing the
levels for two TX lanes.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211006204937.30774-10-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
parent 31e914a2

drivers/gpu/drm/i915/display/intel_ddi.c

+12 −1
Original line number Diff line number Diff line
@@ -1164,7 +1164,6 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 
{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);

	int level = intel_ddi_level(encoder, crtc_state, 0);

	const struct intel_ddi_buf_trans *trans;

	int n_entries, ln;

	u32 val;
@@ -1189,12 +1188,18 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 


	/* Program MG_TX_SWINGCTRL with values from vswing table */

	for (ln = 0; ln < 2; ln++) {

		int level;



		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);



		val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));

		val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;

		val |= CRI_TXDEEMPH_OVERRIDE_17_12(

			trans->entries[level].mg.cri_txdeemph_override_17_12);

		intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);



		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);



		val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));

		val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;

		val |= CRI_TXDEEMPH_OVERRIDE_17_12(
@@ -1204,6 +1209,10 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 


	/* Program MG_TX_DRVCTRL with values from vswing table */

	for (ln = 0; ln < 2; ln++) {

		int level;



		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);



		val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));

		val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |

			 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
@@ -1214,6 +1223,8 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 
			CRI_TXDEEMPH_OVERRIDE_EN;

		intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);



		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);



		val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));

		val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |

			 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);