Commit 30567925 authored by Alexander Stein's avatar Alexander Stein Committed by Shawn Guo
Browse files

arm64: dts: freescale: imx8-ss-dma: Fix edma3's location 



Sort nodes by base address. edma3 comes later in the memory map.

Signed-off-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent c123e12f

arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi

+23 −23
Original line number Diff line number Diff line
@@ -192,29 +192,6 @@ edma2: dma-controller@5a1f0000 { 
				<&pd IMX_SC_R_DMA_2_CH15>;

	};



	edma3: dma-controller@5a9f0000 {

		compatible = "fsl,imx8qm-edma";

		reg = <0x5a9f0000 0x90000>;

		#dma-cells = <3>;

		dma-channels = <8>;

		interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&pd IMX_SC_R_DMA_3_CH0>,

				<&pd IMX_SC_R_DMA_3_CH1>,

				<&pd IMX_SC_R_DMA_3_CH2>,

				<&pd IMX_SC_R_DMA_3_CH3>,

				<&pd IMX_SC_R_DMA_3_CH4>,

				<&pd IMX_SC_R_DMA_3_CH5>,

				<&pd IMX_SC_R_DMA_3_CH6>,

				<&pd IMX_SC_R_DMA_3_CH7>;

	};



	spi0_lpcg: clock-controller@5a400000 {

		compatible = "fsl,imx8qxp-lpcg";

		reg = <0x5a400000 0x10000>;
@@ -460,6 +437,29 @@ flexcan3: can@5a8f0000 { 
		status = "disabled";

	};



	edma3: dma-controller@5a9f0000 {

		compatible = "fsl,imx8qm-edma";

		reg = <0x5a9f0000 0x90000>;

		#dma-cells = <3>;

		dma-channels = <8>;

		interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&pd IMX_SC_R_DMA_3_CH0>,

				<&pd IMX_SC_R_DMA_3_CH1>,

				<&pd IMX_SC_R_DMA_3_CH2>,

				<&pd IMX_SC_R_DMA_3_CH3>,

				<&pd IMX_SC_R_DMA_3_CH4>,

				<&pd IMX_SC_R_DMA_3_CH5>,

				<&pd IMX_SC_R_DMA_3_CH6>,

				<&pd IMX_SC_R_DMA_3_CH7>;

	};



	i2c0_lpcg: clock-controller@5ac00000 {

		compatible = "fsl,imx8qxp-lpcg";

		reg = <0x5ac00000 0x10000>;