Commit 306cbcc6 authored by Clay King's avatar Clay King Committed by Alex Deucher
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drm/amd/display: incorrect conditions for failing dto calculations 



[Why & How]
Previously, when calculating dto phase, we would incorrectly fail when phase
<=0 without additionally checking for the integer value. This meant that
calculations would incorrectly fail when the desired pixel clock was an exact
multiple of the reference clock.

Reviewed-by: default avatarDillon Varone <dillon.varone@amd.com>
Signed-off-by: default avatarClay King <clayking@amd.com>
Signed-off-by: default avatarAlex Hung <alex.hung@amd.com>
Tested-by: default avatarDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cf49a454

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

+1 −1
Original line number Diff line number Diff line
@@ -619,7 +619,7 @@ void dccg401_set_dp_dto( 
		dto_integer = div_u64(params->pixclk_hz, dto_modulo_hz);

		dto_phase_hz = params->pixclk_hz - dto_integer * dto_modulo_hz;



		if (dto_phase_hz <= 0) {

		if (dto_phase_hz <= 0 && dto_integer <= 0) {

			/* negative pixel rate should never happen */

			BREAK_TO_DEBUGGER();

			return;