Commit 3072a24c authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Introduce crtc_state->enhanced_framing 



Track DP enhanced framing properly in the crtc state instead
of relying just on the cached DPCD everywhere, and hook it
up into the state check and dump.

v2: Actually set enhanced_framing in .compute_config()

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230503113659.16305-1-ville.syrjala@linux.intel.com


Reviewed-by: default avatarLuca Coelho <luciano.coelho@intel.com>
parent a7891a0a

drivers/gpu/drm/i915/display/g4x_dp.c

+8 −2
Original line number Diff line number Diff line
@@ -141,7 +141,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder, 


		intel_de_rmw(dev_priv, TRANS_DP_CTL(crtc->pipe),

			     TRANS_DP_ENH_FRAMING,

			     drm_dp_enhanced_frame_cap(intel_dp->dpcd) ?

			     pipe_config->enhanced_framing ?

			     TRANS_DP_ENH_FRAMING : 0);

	} else {

		if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
@@ -153,7 +153,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder, 
			intel_dp->DP |= DP_SYNC_VS_HIGH;

		intel_dp->DP |= DP_LINK_TRAIN_OFF;



		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))

		if (pipe_config->enhanced_framing)

			intel_dp->DP |= DP_ENHANCED_FRAMING;



		if (IS_CHERRYVIEW(dev_priv))
@@ -351,6 +351,9 @@ static void intel_dp_get_config(struct intel_encoder *encoder, 
		u32 trans_dp = intel_de_read(dev_priv,

					     TRANS_DP_CTL(crtc->pipe));



		if (trans_dp & TRANS_DP_ENH_FRAMING)

			pipe_config->enhanced_framing = true;



		if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)

			flags |= DRM_MODE_FLAG_PHSYNC;

		else
@@ -361,6 +364,9 @@ static void intel_dp_get_config(struct intel_encoder *encoder, 
		else

			flags |= DRM_MODE_FLAG_NVSYNC;

	} else {

		if (tmp & DP_ENHANCED_FRAMING)

			pipe_config->enhanced_framing = true;



		if (tmp & DP_SYNC_HS_HIGH)

			flags |= DRM_MODE_FLAG_PHSYNC;

		else

drivers/gpu/drm/i915/display/intel_crt.c

+2 −0
Original line number Diff line number Diff line
@@ -451,6 +451,8 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder, 
	/* FDI must always be 2.7 GHz */

	pipe_config->port_clock = 135000 * 2;



	pipe_config->enhanced_framing = true;



	adjusted_mode->crtc_clock = lpt_iclkip(pipe_config);



	return 0;

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

+3 −2
Original line number Diff line number Diff line
@@ -258,8 +258,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, 
		intel_dump_m_n_config(pipe_config, "dp m2_n2",

				      pipe_config->lane_count,

				      &pipe_config->dp_m2_n2);

		drm_dbg_kms(&i915->drm, "fec: %s\n",

			    str_enabled_disabled(pipe_config->fec_enable));

		drm_dbg_kms(&i915->drm, "fec: %s, enhanced framing: %s\n",

			    str_enabled_disabled(pipe_config->fec_enable),

			    str_enabled_disabled(pipe_config->enhanced_framing));

	}



	drm_dbg_kms(&i915->drm, "framestart delay: %d, MSA timing delay: %d\n",

drivers/gpu/drm/i915/display/intel_ddi.c

+9 −2
Original line number Diff line number Diff line
@@ -3432,7 +3432,7 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 
		dp_tp_ctl |= DP_TP_CTL_MODE_MST;

	} else {

		dp_tp_ctl |= DP_TP_CTL_MODE_SST;

		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))

		if (crtc_state->enhanced_framing)

			dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;

	}

	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
@@ -3489,7 +3489,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 
		dp_tp_ctl |= DP_TP_CTL_MODE_MST;

	} else {

		dp_tp_ctl |= DP_TP_CTL_MODE_SST;

		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))

		if (crtc_state->enhanced_framing)

			dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;

	}

	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
@@ -3724,6 +3724,10 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 
		intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder,

					       &pipe_config->dp_m2_n2);



		pipe_config->enhanced_framing =

			intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) &

			DP_TP_CTL_ENHANCED_FRAME_ENABLE;



		if (DISPLAY_VER(dev_priv) >= 11)

			pipe_config->fec_enable =

				intel_de_read(dev_priv,
@@ -3740,6 +3744,9 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 
		if (!HAS_DP20(dev_priv)) {

			/* FDI */

			pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);

			pipe_config->enhanced_framing =

				intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) &

				DP_TP_CTL_ENHANCED_FRAME_ENABLE;

			break;

		}

		fallthrough; /* 128b/132b */

drivers/gpu/drm/i915/display/intel_display.c

+1 −0
Original line number Diff line number Diff line
@@ -5210,6 +5210,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, 
	PIPE_CONF_CHECK_BOOL(hdmi_scrambling);

	PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);

	PIPE_CONF_CHECK_BOOL(has_infoframe);

	PIPE_CONF_CHECK_BOOL(enhanced_framing);

	PIPE_CONF_CHECK_BOOL(fec_enable);



	PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);