dt-bindings: display/msm: Add Qualcomm SAR2130P (3096209b) · Commits · git / linux-net

Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml

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		# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/display/msm/qcom,sar2130p-mdss.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Qualcomm SAR2130P Display MDSS

		maintainers:
		- Dmitry Baryshkov <lumag@kernel.org>

		description:
		SAR2310P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
		DPU display controller, DSI and DP interfaces etc.

		$ref: /schemas/display/msm/mdss-common.yaml#

		properties:
		compatible:
		const: qcom,sar2130p-mdss

		clocks:
		items:
		- description: Display MDSS AHB
		- description: Display AHB
		- description: Display hf AXI
		- description: Display core

		iommus:
		maxItems: 1

		interconnects:
		items:
		- description: Interconnect path from mdp0 port to the data bus
		- description: Interconnect path from CPU to the reg bus

		interconnect-names:
		items:
		- const: mdp0-mem
		- const: cpu-cfg

		patternProperties:
		"^display-controller@[0-9a-f]+$":
		type: object
		additionalProperties: true
		properties:
		compatible:
		const: qcom,sar2130p-dpu

		"^displayport-controller@[0-9a-f]+$":
		type: object
		additionalProperties: true
		properties:
		compatible:
		contains:
		const: qcom,sar2130p-dp

		"^dsi@[0-9a-f]+$":
		type: object
		additionalProperties: true
		properties:
		compatible:
		contains:
		const: qcom,sar2130p-dsi-ctrl

		"^phy@[0-9a-f]+$":
		type: object
		additionalProperties: true
		properties:
		compatible:
		const: qcom,sar2130p-dsi-phy-5nm

		required:
		- compatible

		unevaluatedProperties: false

		examples:
		- \|
		#include <dt-bindings/interrupt-controller/arm-gic.h>
		#include <dt-bindings/power/qcom,rpmhpd.h>
		#include <dt-bindings/phy/phy-qcom-qmp.h>

		display-subsystem@ae00000 {
		compatible = "qcom,sar2130p-mdss";
		reg = <0x0ae00000 0x1000>;
		reg-names = "mdss";

		interconnects = <&mmss_noc_master_mdp &mc_virt_slave_ebi1>,
		<&gem_noc_master_appss_proc &config_noc_slave_display_cfg>;
		interconnect-names = "mdp0-mem", "cpu-cfg";

		resets = <&dispcc_disp_cc_mdss_core_bcr>;

		power-domains = <&dispcc_mdss_gdsc>;

		clocks = <&dispcc_disp_cc_mdss_ahb_clk>,
		<&gcc_gcc_disp_ahb_clk>,
		<&gcc_gcc_disp_hf_axi_clk>,
		<&dispcc_disp_cc_mdss_mdp_clk>;
		clock-names = "iface", "bus", "nrt_bus", "core";

		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <1>;

		iommus = <&apps_smmu 0x1c00 0x2>;

		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		display-controller@ae01000 {
		compatible = "qcom,sar2130p-dpu";
		reg = <0x0ae01000 0x8f000>,
		<0x0aeb0000 0x2008>;
		reg-names = "mdp", "vbif";

		clocks = <&gcc_gcc_disp_ahb_clk>,
		<&gcc_gcc_disp_hf_axi_clk>,
		<&dispcc_disp_cc_mdss_ahb_clk>,
		<&dispcc_disp_cc_mdss_mdp_lut_clk>,
		<&dispcc_disp_cc_mdss_mdp_clk>,
		<&dispcc_disp_cc_mdss_vsync_clk>;
		clock-names = "bus",
		"nrt_bus",
		"iface",
		"lut",
		"core",
		"vsync";

		assigned-clocks = <&dispcc_disp_cc_mdss_vsync_clk>;
		assigned-clock-rates = <19200000>;

		operating-points-v2 = <&mdp_opp_table>;
		power-domains = <&rpmhpd RPMHPD_MMCX>;

		interrupt-parent = <&mdss>;
		interrupts = <0>;

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;

		dpu_intf0_out: endpoint {
		remote-endpoint = <&mdss_dp0_in>;
		};
		};

		port@1 {
		reg = <1>;

		dpu_intf1_out: endpoint {
		remote-endpoint = <&mdss_dsi0_in>;
		};
		};

		port@2 {
		reg = <2>;

		dpu_intf2_out: endpoint {
		remote-endpoint = <&mdss_dsi1_in>;
		};
		};
		};

		mdp_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-200000000 {
		opp-hz = /bits/ 64 <200000000>;
		required-opps = <&rpmhpd_opp_low_svs>;
		};

		opp-325000000 {
		opp-hz = /bits/ 64 <325000000>;
		required-opps = <&rpmhpd_opp_svs>;
		};

		opp-375000000 {
		opp-hz = /bits/ 64 <375000000>;
		required-opps = <&rpmhpd_opp_svs_l1>;
		};

		opp-514000000 {
		opp-hz = /bits/ 64 <514000000>;
		required-opps = <&rpmhpd_opp_nom>;
		};
		};
		};

		displayport-controller@ae90000 {
		compatible = "qcom,sar2130p-dp",
		"qcom,sm8350-dp";
		reg = <0xae90000 0x200>,
		<0xae90200 0x200>,
		<0xae90400 0xc00>,
		<0xae91000 0x400>,
		<0xae91400 0x400>;

		interrupt-parent = <&mdss>;
		interrupts = <12>;
		clocks = <&dispcc_disp_cc_mdss_ahb_clk>,
		<&dispcc_disp_cc_mdss_dptx0_aux_clk>,
		<&dispcc_disp_cc_mdss_dptx0_link_clk>,
		<&dispcc_disp_cc_mdss_dptx0_link_intf_clk>,
		<&dispcc_disp_cc_mdss_dptx0_pixel0_clk>;
		clock-names = "core_iface",
		"core_aux",
		"ctrl_link",
		"ctrl_link_iface",
		"stream_pixel";

		assigned-clocks = <&dispcc_disp_cc_mdss_dptx0_link_clk_src>,
		<&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>;
		assigned-clock-parents = <&usb_dp_qmpphy_QMP_USB43DP_DP_LINK_CLK>,
		<&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DIV_CLK>;

		phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
		phy-names = "dp";

		#sound-dai-cells = <0>;

		operating-points-v2 = <&dp_opp_table>;
		power-domains = <&rpmhpd RPMHPD_MMCX>;

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		mdss_dp0_in: endpoint {
		remote-endpoint = <&dpu_intf0_out>;
		};
		};

		port@1 {
		reg = <1>;
		mdss_dp0_out: endpoint {
		remote-endpoint = <&usb_dp_qmpphy_dp_in>;
		};
		};
		};

		dp_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-162000000 {
		opp-hz = /bits/ 64 <162000000>;
		required-opps = <&rpmhpd_opp_low_svs_d1>;
		};

		opp-270000000 {
		opp-hz = /bits/ 64 <270000000>;
		required-opps = <&rpmhpd_opp_low_svs>;
		};

		opp-540000000 {
		opp-hz = /bits/ 64 <540000000>;
		required-opps = <&rpmhpd_opp_svs_l1>;
		};

		opp-810000000 {
		opp-hz = /bits/ 64 <810000000>;
		required-opps = <&rpmhpd_opp_nom>;
		};
		};
		};

		dsi@ae94000 {
		compatible = "qcom,sar2130p-dsi-ctrl",
		"qcom,mdss-dsi-ctrl";
		reg = <0x0ae94000 0x400>;
		reg-names = "dsi_ctrl";

		interrupt-parent = <&mdss>;
		interrupts = <4>;

		clocks = <&dispcc_disp_cc_mdss_byte0_clk>,
		<&dispcc_disp_cc_mdss_byte0_intf_clk>,
		<&dispcc_disp_cc_mdss_pclk0_clk>,
		<&dispcc_disp_cc_mdss_esc0_clk>,
		<&dispcc_disp_cc_mdss_ahb_clk>,
		<&gcc_gcc_disp_hf_axi_clk>;
		clock-names = "byte",
		"byte_intf",
		"pixel",
		"core",
		"iface",
		"bus";

		assigned-clocks = <&dispcc_disp_cc_mdss_byte0_clk_src>,
		<&dispcc_disp_cc_mdss_pclk0_clk_src>;
		assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;

		operating-points-v2 = <&dsi_opp_table>;
		power-domains = <&rpmhpd RPMHPD_MMCX>;

		phys = <&mdss_dsi0_phy>;
		phy-names = "dsi";

		#address-cells = <1>;
		#size-cells = <0>;

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;

		mdss_dsi0_in: endpoint {
		remote-endpoint = <&dpu_intf1_out>;
		};
		};

		port@1 {
		reg = <1>;

		mdss_dsi0_out: endpoint {
		};
		};
		};

		dsi_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-187500000 {
		opp-hz = /bits/ 64 <187500000>;
		required-opps = <&rpmhpd_opp_low_svs>;
		};

		opp-300000000 {
		opp-hz = /bits/ 64 <300000000>;
		required-opps = <&rpmhpd_opp_svs>;
		};

		opp-358000000 {
		opp-hz = /bits/ 64 <358000000>;
		required-opps = <&rpmhpd_opp_svs_l1>;
		};
		};
		};

		mdss_dsi0_phy: phy@ae94400 {
		compatible = "qcom,sar2130p-dsi-phy-5nm";
		reg = <0x0ae95000 0x200>,
		<0x0ae95200 0x280>,
		<0x0ae95500 0x400>;
		reg-names = "dsi_phy",
		"dsi_phy_lane",
		"dsi_pll";

		#clock-cells = <1>;
		#phy-cells = <0>;

		clocks = <&dispcc_disp_cc_mdss_ahb_clk>,
		<&rpmhcc_rpmh_cxo_clk>;
		clock-names = "iface", "ref";
		};

		dsi@ae96000 {
		compatible = "qcom,sar2130p-dsi-ctrl",
		"qcom,mdss-dsi-ctrl";
		reg = <0x0ae96000 0x400>;
		reg-names = "dsi_ctrl";

		interrupt-parent = <&mdss>;
		interrupts = <5>;

		clocks = <&dispcc_disp_cc_mdss_byte1_clk>,
		<&dispcc_disp_cc_mdss_byte1_intf_clk>,
		<&dispcc_disp_cc_mdss_pclk1_clk>,
		<&dispcc_disp_cc_mdss_esc1_clk>,
		<&dispcc_disp_cc_mdss_ahb_clk>,
		<&gcc_gcc_disp_hf_axi_clk>;
		clock-names = "byte",
		"byte_intf",
		"pixel",
		"core",
		"iface",
		"bus";

		assigned-clocks = <&dispcc_disp_cc_mdss_byte1_clk_src>,
		<&dispcc_disp_cc_mdss_pclk1_clk_src>;
		assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;

		operating-points-v2 = <&dsi_opp_table>;
		power-domains = <&rpmhpd RPMHPD_MMCX>;

		phys = <&mdss_dsi1_phy>;
		phy-names = "dsi";

		#address-cells = <1>;
		#size-cells = <0>;

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;

		mdss_dsi1_in: endpoint {
		remote-endpoint = <&dpu_intf2_out>;
		};
		};

		port@1 {
		reg = <1>;

		mdss_dsi1_out: endpoint {
		};
		};
		};
		};

		mdss_dsi1_phy: phy@ae97000 {
		compatible = "qcom,sar2130p-dsi-phy-5nm";
		reg = <0x0ae97000 0x200>,
		<0x0ae97200 0x280>,
		<0x0ae97500 0x400>;
		reg-names = "dsi_phy",
		"dsi_phy_lane",
		"dsi_pll";

		#clock-cells = <1>;
		#phy-cells = <0>;

		clocks = <&dispcc_disp_cc_mdss_ahb_clk>,
		<&rpmhcc_rpmh_cxo_clk>;
		clock-names = "iface", "ref";
		};
		};
		...