Commit 30d8b7d4 authored by Elaine Zhang's avatar Elaine Zhang Committed by Heiko Stuebner
Browse files

clk: rockchip: Add MUXTBL variant 



Add a clock branch consisting of a mux with non-standard
select values. The parent in Mux table is sorted by priority.
Use clk_register_mux_table() to register such a mux-clock.

Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: default avatarJagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20220907160207.3845791-3-jagan@edgeble.ai


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 1c23f9e6

drivers/clk/rockchip/clk.c

+21 −6
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ static struct clk *rockchip_clk_register_branch(const char *name, 
		const char *const *parent_names, u8 num_parents,

		void __iomem *base,

		int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,

		u32 *mux_table,

		int div_offset, u8 div_shift, u8 div_width, u8 div_flags,

		struct clk_div_table *div_table, int gate_offset,

		u8 gate_shift, u8 gate_flags, unsigned long flags,
@@ -62,6 +63,7 @@ static struct clk *rockchip_clk_register_branch(const char *name, 
		mux->shift = mux_shift;

		mux->mask = BIT(mux_width) - 1;

		mux->flags = mux_flags;

		mux->table = mux_table;

		mux->lock = lock;

		mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops

							: &clk_mux_ops;
@@ -270,6 +272,8 @@ static struct clk *rockchip_clk_register_frac_branch( 
		frac_mux->shift = child->mux_shift;

		frac_mux->mask = BIT(child->mux_width) - 1;

		frac_mux->flags = child->mux_flags;

		if (child->mux_table)

			frac_mux->table = child->mux_table;

		frac_mux->lock = lock;

		frac_mux->hw.init = &init;
@@ -444,9 +448,19 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, 
		/* catch simple muxes */

		switch (list->branch_type) {

		case branch_mux:

			if (list->mux_table)

				clk = clk_register_mux_table(NULL, list->name,

					list->parent_names, list->num_parents,

					flags,

					ctx->reg_base + list->muxdiv_offset,

					list->mux_shift, list->mux_width,

					list->mux_flags, list->mux_table,

					&ctx->lock);

			else

				clk = clk_register_mux(NULL, list->name,

					list->parent_names, list->num_parents,

				flags, ctx->reg_base + list->muxdiv_offset,

					flags,

					ctx->reg_base + list->muxdiv_offset,

					list->mux_shift, list->mux_width,

					list->mux_flags, &ctx->lock);

			break;
@@ -506,7 +520,8 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, 
				ctx->reg_base, list->muxdiv_offset,

				list->mux_shift,

				list->mux_width, list->mux_flags,

				list->div_offset, list->div_shift, list->div_width,

				list->mux_table, list->div_offset,

				list->div_shift, list->div_width,

				list->div_flags, list->div_table,

				list->gate_offset, list->gate_shift,

				list->gate_flags, flags, &ctx->lock);

drivers/clk/rockchip/clk.h

+17 −0
Original line number Diff line number Diff line
@@ -448,6 +448,7 @@ struct rockchip_clk_branch { 
	u8				mux_shift;

	u8				mux_width;

	u8				mux_flags;

	u32				*mux_table;

	int				div_offset;

	u8				div_shift;

	u8				div_width;
@@ -680,6 +681,22 @@ struct rockchip_clk_branch { 
		.gate_offset	= -1,				\

	}



#define MUXTBL(_id, cname, pnames, f, o, s, w, mf, mt)		\

	{							\

		.id		= _id,				\

		.branch_type	= branch_mux,			\

		.name		= cname,			\

		.parent_names	= pnames,			\

		.num_parents	= ARRAY_SIZE(pnames),		\

		.flags		= f,				\

		.muxdiv_offset	= o,				\

		.mux_shift	= s,				\

		.mux_width	= w,				\

		.mux_flags	= mf,				\

		.gate_offset	= -1,				\

		.mux_table	= mt,				\

	}



#define MUXGRF(_id, cname, pnames, f, o, s, w, mf)		\

	{							\

		.id		= _id,				\