Commit 30eb191c authored by Sergey Matyukevich's avatar Sergey Matyukevich Committed by Paul Walmsley
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selftests: riscv: verify ptrace rejects invalid vector csr inputs 



Add a test to v_ptrace test suite to verify that ptrace rejects the
invalid input combinations of vector csr registers. Use kselftest
fixture variants to create multiple invalid inputs for the test.

Signed-off-by: default avatarSergey Matyukevich <geomatsi@gmail.com>
Tested-by: default avatarAndy Chiu <andybnac@gmail.com>
Link: https://patch.msgid.link/20251214163537.1054292-9-geomatsi@gmail.com


[pjw@kernel.org: cleaned up some checkpatch issues]
Signed-off-by: default avatarPaul Walmsley <pjw@kernel.org>
parent 3789d5ee

tools/testing/selftests/riscv/vector/validate_v_ptrace.c

+317 −0
Original line number Diff line number Diff line
@@ -334,4 +334,321 @@ TEST(ptrace_v_syscall_clobbering) 
	}

}



FIXTURE(v_csr_invalid)

{

};



FIXTURE_SETUP(v_csr_invalid)

{

}



FIXTURE_TEARDOWN(v_csr_invalid)

{

}



#define VECTOR_1_0		BIT(0)

#define XTHEAD_VECTOR_0_7	BIT(1)



#define vector_test(x)		((x) & VECTOR_1_0)

#define xthead_test(x)		((x) & XTHEAD_VECTOR_0_7)



/* modifications of the initial vsetvli settings */

FIXTURE_VARIANT(v_csr_invalid)

{

	unsigned long vstart;

	unsigned long vl;

	unsigned long vtype;

	unsigned long vcsr;

	unsigned long vlenb_mul;

	unsigned long vlenb_min;

	unsigned long vlenb_max;

	unsigned long spec;

};



/* unexpected vlenb value */

FIXTURE_VARIANT_ADD(v_csr_invalid, new_vlenb)

{

	.vstart = 0x0,

	.vl = 0x0,

	.vtype = 0x3,

	.vcsr = 0x0,

	.vlenb_mul = 0x2,

	.vlenb_min = 0x0,

	.vlenb_max = 0x0,

	.spec = VECTOR_1_0 | XTHEAD_VECTOR_0_7,

};



/* invalid reserved bits in vcsr */

FIXTURE_VARIANT_ADD(v_csr_invalid, vcsr_invalid_reserved_bits)

{

	.vstart = 0x0,

	.vl = 0x0,

	.vtype = 0x3,

	.vcsr = 0x1UL << 8,

	.vlenb_mul = 0x1,

	.vlenb_min = 0x0,

	.vlenb_max = 0x0,

	.spec = VECTOR_1_0 | XTHEAD_VECTOR_0_7,

};



/* invalid reserved bits in vtype */

FIXTURE_VARIANT_ADD(v_csr_invalid, vtype_invalid_reserved_bits)

{

	.vstart = 0x0,

	.vl = 0x0,

	.vtype = (0x1UL << 8) | 0x3,

	.vcsr = 0x0,

	.vlenb_mul = 0x1,

	.vlenb_min = 0x0,

	.vlenb_max = 0x0,

	.spec = VECTOR_1_0 | XTHEAD_VECTOR_0_7,

};



/* set vill bit */

FIXTURE_VARIANT_ADD(v_csr_invalid, invalid_vill_bit)

{

	.vstart = 0x0,

	.vl = 0x0,

	.vtype = (0x1UL << (__riscv_xlen - 1)) | 0x3,

	.vcsr = 0x0,

	.vlenb_mul = 0x1,

	.vlenb_min = 0x0,

	.vlenb_max = 0x0,

	.spec = VECTOR_1_0 | XTHEAD_VECTOR_0_7,

};



/* reserved vsew value: vsew > 3 */

FIXTURE_VARIANT_ADD(v_csr_invalid, reserved_vsew)

{

	.vstart = 0x0,

	.vl = 0x0,

	.vtype = 0x4UL << 3,

	.vcsr = 0x0,

	.vlenb_mul = 0x1,

	.vlenb_min = 0x0,

	.vlenb_max = 0x0,

	.spec = VECTOR_1_0,

};



/* XTheadVector: unsupported non-zero VEDIV value */

FIXTURE_VARIANT_ADD(v_csr_invalid, reserved_vediv)

{

	.vstart = 0x0,

	.vl = 0x0,

	.vtype = 0x3UL << 5,

	.vcsr = 0x0,

	.vlenb_mul = 0x1,

	.vlenb_min = 0x0,

	.vlenb_max = 0x0,

	.spec = XTHEAD_VECTOR_0_7,

};



/* reserved vlmul value: vlmul == 4 */

FIXTURE_VARIANT_ADD(v_csr_invalid, reserved_vlmul)

{

	.vstart = 0x0,

	.vl = 0x0,

	.vtype = 0x4,

	.vcsr = 0x0,

	.vlenb_mul = 0x1,

	.vlenb_min = 0x0,

	.vlenb_max = 0x0,

	.spec = VECTOR_1_0,

};



/* invalid fractional LMUL for VLEN <= 256: LMUL= 1/8, SEW = 64 */

FIXTURE_VARIANT_ADD(v_csr_invalid, frac_lmul1)

{

	.vstart = 0x0,

	.vl = 0x0,

	.vtype = 0x1d,

	.vcsr = 0x0,

	.vlenb_mul = 0x1,

	.vlenb_min = 0x0,

	.vlenb_max = 0x20,

	.spec = VECTOR_1_0,

};



/* invalid integral LMUL for VLEN <= 16: LMUL= 2, SEW = 64 */

FIXTURE_VARIANT_ADD(v_csr_invalid, int_lmul1)

{

	.vstart = 0x0,

	.vl = 0x0,

	.vtype = 0x19,

	.vcsr = 0x0,

	.vlenb_mul = 0x1,

	.vlenb_min = 0x0,

	.vlenb_max = 0x2,

	.spec = VECTOR_1_0,

};



/* XTheadVector: invalid integral LMUL for VLEN <= 16: LMUL= 2, SEW = 64 */

FIXTURE_VARIANT_ADD(v_csr_invalid, int_lmul2)

{

	.vstart = 0x0,

	.vl = 0x0,

	.vtype = 0xd,

	.vcsr = 0x0,

	.vlenb_mul = 0x1,

	.vlenb_min = 0x0,

	.vlenb_max = 0x2,

	.spec = XTHEAD_VECTOR_0_7,

};



/* invalid VL for VLEN <= 128: LMUL= 2, SEW = 64, VL = 8 */

FIXTURE_VARIANT_ADD(v_csr_invalid, vl1)

{

	.vstart = 0x0,

	.vl = 0x8,

	.vtype = 0x19,

	.vcsr = 0x0,

	.vlenb_mul = 0x1,

	.vlenb_min = 0x0,

	.vlenb_max = 0x10,

	.spec = VECTOR_1_0,

};



/* XTheadVector: invalid VL for VLEN <= 128: LMUL= 2, SEW = 64, VL = 8 */

FIXTURE_VARIANT_ADD(v_csr_invalid, vl2)

{

	.vstart = 0x0,

	.vl = 0x8,

	.vtype = 0xd,

	.vcsr = 0x0,

	.vlenb_mul = 0x1,

	.vlenb_min = 0x0,

	.vlenb_max = 0x10,

	.spec = XTHEAD_VECTOR_0_7,

};



TEST_F(v_csr_invalid, ptrace_v_invalid_values)

{

	unsigned long vlenb;

	pid_t pid;



	if (!is_vector_supported() && !is_xtheadvector_supported())

		SKIP(return, "Vectors not supported");



	if (is_vector_supported() && !vector_test(variant->spec))

		SKIP(return, "Test not supported for Vector");



	if (is_xtheadvector_supported() && !xthead_test(variant->spec))

		SKIP(return, "Test not supported for XTheadVector");



	vlenb = get_vr_len();



	if (variant->vlenb_min) {

		if (vlenb < variant->vlenb_min)

			SKIP(return, "This test does not support VLEN < %lu\n",

			     variant->vlenb_min * 8);

	}



	if (variant->vlenb_max) {

		if (vlenb > variant->vlenb_max)

			SKIP(return, "This test does not support VLEN > %lu\n",

			     variant->vlenb_max * 8);

	}



	chld_lock = 1;

	pid = fork();

	ASSERT_LE(0, pid)

		TH_LOG("fork: %m");



	if (pid == 0) {

		unsigned long vl;



		while (chld_lock == 1)

			asm volatile("" : : "g"(chld_lock) : "memory");



		if (is_xtheadvector_supported()) {

			asm volatile (

				// 0 | zimm[10:0] | rs1 | 1 1 1 | rd |1010111| vsetvli

				// vsetvli	t4, x0, e16, m2, d1

				".4byte		0b00000000010100000111111011010111\n"

				"mv		%[new_vl], t4\n"

				: [new_vl] "=r" (vl) : : "t4");

		} else {

			asm volatile (

				".option push\n"

				".option arch, +zve32x\n"

				"vsetvli %[new_vl], x0, e16, m2, tu, mu\n"

				".option pop\n"

				: [new_vl] "=r"(vl) : : );

		}



		while (1) {

			asm volatile (

				".option push\n"

				".option norvc\n"

				"ebreak\n"

				"nop\n"

				".option pop\n");

		}

	} else {

		struct __riscv_v_regset_state *regset_data;

		size_t regset_size;

		struct iovec iov;

		int status;

		int ret;



		/* attach */



		ASSERT_EQ(0, ptrace(PTRACE_ATTACH, pid, NULL, NULL));

		ASSERT_EQ(pid, waitpid(pid, &status, 0));

		ASSERT_TRUE(WIFSTOPPED(status));



		/* unlock */



		ASSERT_EQ(0, ptrace(PTRACE_POKEDATA, pid, &chld_lock, 0));



		/* resume and wait for the 1st ebreak */



		ASSERT_EQ(0, ptrace(PTRACE_CONT, pid, NULL, NULL));

		ASSERT_EQ(pid, waitpid(pid, &status, 0));

		ASSERT_TRUE(WIFSTOPPED(status));



		/* read tracee vector csr regs using ptrace GETREGSET */



		regset_size = sizeof(*regset_data) + vlenb * 32;

		regset_data = calloc(1, regset_size);



		iov.iov_base = regset_data;

		iov.iov_len = regset_size;



		ASSERT_EQ(0, ptrace(PTRACE_GETREGSET, pid, NT_RISCV_VECTOR, &iov));



		/* verify initial vsetvli settings */



		if (is_xtheadvector_supported())

			EXPECT_EQ(5UL, regset_data->vtype);

		else

			EXPECT_EQ(9UL, regset_data->vtype);



		EXPECT_EQ(regset_data->vlenb, regset_data->vl);

		EXPECT_EQ(vlenb, regset_data->vlenb);

		EXPECT_EQ(0UL, regset_data->vstart);

		EXPECT_EQ(0UL, regset_data->vcsr);



		/* apply invalid settings from fixture variants */



		regset_data->vlenb *= variant->vlenb_mul;

		regset_data->vstart = variant->vstart;

		regset_data->vtype = variant->vtype;

		regset_data->vcsr = variant->vcsr;

		regset_data->vl = variant->vl;



		iov.iov_base = regset_data;

		iov.iov_len = regset_size;



		errno = 0;

		ret = ptrace(PTRACE_SETREGSET, pid, NT_RISCV_VECTOR, &iov);

		ASSERT_EQ(errno, EINVAL);

		ASSERT_EQ(ret, -1);



		/* cleanup */



		ASSERT_EQ(0, kill(pid, SIGKILL));

	}

}



TEST_HARNESS_MAIN