Commit 30eb41f5 authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amdgpu: Use firmware supported NPS modes 



If firmware supported NPS modes are available through CAP register, use
those values for supported NPS modes.

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b2a9e562

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+26 −10
Original line number Diff line number Diff line
@@ -1594,11 +1594,26 @@ static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) 


static void gmc_v9_0_init_nps_details(struct amdgpu_device *adev)

{

	enum amdgpu_memory_partition mode;

	uint32_t supp_modes;

	int i;



	adev->gmc.supported_nps_modes = 0;



	if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU))

		return;



	mode = gmc_v9_0_get_memory_partition(adev, &supp_modes);



	/* Mode detected by hardware and supported modes available */

	if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && supp_modes) {

		for (i = AMDGPU_NPS1_PARTITION_MODE;

		     supp_modes && i <= AMDGPU_NPS8_PARTITION_MODE; i++) {

			if (supp_modes & BIT(i - 1))

				adev->gmc.supported_nps_modes |= BIT(i);

			supp_modes &= supp_modes - 1;

		}

	} else {

		/*TODO: Check PSP version also which supports NPS switch. Otherwise keep

	 * supported modes as 0.

	 */
@@ -1613,6 +1628,7 @@ static void gmc_v9_0_init_nps_details(struct amdgpu_device *adev) 
			break;

		}

	}

}



static int gmc_v9_0_early_init(struct amdgpu_ip_block *ip_block)

{