Commit 30f93868 authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/misc' into for-next/core

* for-next/misc:
  arm64: Kconfig: Make CPU_BIG_ENDIAN depend on BROKEN
  arm64: Kconfig: Spell out "ARMv9.4" in menuconfig text
  arm64/fpsimd: simplify sme_setup()
parents 7df73a00 1cf89b6b
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+3 −3
Original line number Diff line number Diff line
@@ -1495,7 +1495,7 @@ choice
config CPU_BIG_ENDIAN
	bool "Build big-endian kernel"
	# https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
	depends on AS_IS_GNU || AS_VERSION >= 150000
	depends on (AS_IS_GNU || AS_VERSION >= 150000) && BROKEN
	help
	  Say Y if you plan on running a kernel with a big-endian userspace.

@@ -2220,7 +2220,7 @@ config ARM64_HAFT

endmenu # "ARMv8.9 architectural features"

menu "v9.4 architectural features"
menu "ARMv9.4 architectural features"

config ARM64_GCS
	bool "Enable support for Guarded Control Stack (GCS)"
@@ -2239,7 +2239,7 @@ config ARM64_GCS
	  The feature is detected at runtime, and will remain disabled
	  if the system does not implement the feature.

endmenu # "v9.4 architectural features"
endmenu # "ARMv9.4 architectural features"

config ARM64_SVE
	bool "ARM Scalable Vector Extension support"
+3 −2
Original line number Diff line number Diff line
@@ -1265,6 +1265,8 @@ void __init sme_setup(void)
	if (!system_supports_sme())
		return;

	min_bit = find_last_bit(info->vq_map, SVE_VQ_MAX);

	/*
	 * SME doesn't require any particular vector length be
	 * supported but it does require at least one.  We should have
@@ -1272,9 +1274,8 @@ void __init sme_setup(void)
	 * let's double check here.  The bitmap is SVE_VQ_MAP sized for
	 * sharing with SVE.
	 */
	WARN_ON(bitmap_empty(info->vq_map, SVE_VQ_MAX));
	WARN_ON(min_bit >= SVE_VQ_MAX);

	min_bit = find_last_bit(info->vq_map, SVE_VQ_MAX);
	info->min_vl = sve_vl_from_vq(__bit_to_vq(min_bit));

	max_bit = find_first_bit(info->vq_map, SVE_VQ_MAX);