Commit 3132a9a1 authored by Jagadeesh Kona's avatar Jagadeesh Kona Committed by Bjorn Andersson
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clk: qcom: clk-alpha-pll: Add support for lucid ole pll configure 



Lucid ole pll has as extra RINGOSC_CAL_L field in L register in
addition to the fields that are part of lucid evo pll, hence add
support for lucid ole pll configure function to configure the ole plls.

Signed-off-by: default avatarJagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230707035744.22245-3-quic_jkona@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 9cbc6474

drivers/clk/qcom/clk-alpha-pll.c

+29 −0
Original line number Diff line number Diff line
@@ -271,6 +271,7 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 
#define LUCID_EVO_ENABLE_VOTE_RUN       BIT(25)

#define LUCID_EVO_PLL_L_VAL_MASK        GENMASK(15, 0)

#define LUCID_EVO_PLL_CAL_L_VAL_SHIFT	16

#define LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT	24



/* ZONDA PLL specific */

#define ZONDA_PLL_OUT_MASK	0xf
@@ -2119,6 +2120,34 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma 
}

EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure);



void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				 const struct alpha_pll_config *config)

{

	u32 lval = config->l;



	lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;

	lval |= TRION_PLL_CAL_VAL << LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT;

	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);

	clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);

	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);

	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);

	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);

	clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);

	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);

	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);

	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);

	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);

	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);



	/* Disable PLL output */

	regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);



	/* Set operation mode to STANDBY and de-assert the reset */

	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);

	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);

}

EXPORT_SYMBOL_GPL(clk_lucid_ole_pll_configure);



static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

drivers/clk/qcom/clk-alpha-pll.h

+2 −0
Original line number Diff line number Diff line
@@ -199,6 +199,8 @@ void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 
			     const struct alpha_pll_config *config);

void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				 const struct alpha_pll_config *config);

void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				 const struct alpha_pll_config *config);

void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				  const struct alpha_pll_config *config);

void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,