Commit 3140af2f authored by Jouni Högander's avatar Jouni Högander
Browse files

drm/i915/psr: Write DSC parameters on Selective Update in ET mode 



There are slice row per frame and pic height parameters in DSC that needs
to be configured on every Selective Update in Early Transport mode. Use
helper provided by DSC code to configure these on Selective Update when in
Early Transport mode. Also fill crtc_state->psr2_su_area with full frame
area on full frame update for DSC calculation.

v2: move psr2_su_area under skip_sel_fetch_set_loop label

Bspec: 68927, 71709
Fixes: 467e4e06 ("drm/i915/psr: Enable psr2 early transport as possible")
Cc: <stable@vger.kernel.org> # v6.9+
Signed-off-by: default avatarJouni Högander <jouni.hogander@intel.com>
Reviewed-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20260304113011.626542-5-jouni.hogander@intel.com
parent c8698d61

drivers/gpu/drm/i915/display/intel_psr.c

+10 −0
Original line number Diff line number Diff line
@@ -2623,6 +2623,12 @@ void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, 


	intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),

			   crtc_state->pipe_srcsz_early_tpt);



	if (!crtc_state->dsc.compression_enable)

		return;



	intel_dsc_su_et_parameters_configure(dsb, encoder, crtc_state,

					     drm_rect_height(&crtc_state->psr2_su_area));

}



static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
@@ -3044,6 +3050,10 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 
	}



skip_sel_fetch_set_loop:

	if (full_update)

		clip_area_update(&crtc_state->psr2_su_area, &crtc_state->pipe_src,

				 &crtc_state->pipe_src);



	psr2_man_trk_ctl_calc(crtc_state, full_update);

	crtc_state->pipe_srcsz_early_tpt =

		psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update);