Commit 314b40b3 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvmarm-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD 

KVM/arm64 changes for 6.17, round #1

 - Host driver for GICv5, the next generation interrupt controller for
   arm64, including support for interrupt routing, MSIs, interrupt
   translation and wired interrupts.

 - Use FEAT_GCIE_LEGACY on GICv5 systems to virtualize GICv3 VMs on
   GICv5 hardware, leveraging the legacy VGIC interface.

 - Userspace control of the 'nASSGIcap' GICv3 feature, allowing
   userspace to disable support for SGIs w/o an active state on hardware
   that previously advertised it unconditionally.

 - Map supporting endpoints with cacheable memory attributes on systems
   with FEAT_S2FWB and DIC where KVM no longer needs to perform cache
   maintenance on the address range.

 - Nested support for FEAT_RAS and FEAT_DoubleFault2, allowing the guest
   hypervisor to inject external aborts into an L2 VM and take traps of
   masked external aborts to the hypervisor.

 - Convert more system register sanitization to the config-driven
   implementation.

 - Fixes to the visibility of EL2 registers, namely making VGICv3 system
   registers accessible through the VGIC device instead of the ONE_REG
   vCPU ioctls.

 - Various cleanups and minor fixes.
parents beafd7ec 18ec25dd

Documentation/arch/arm64/booting.rst

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Original line number Diff line number Diff line
@@ -223,6 +223,47 @@ Before jumping into the kernel, the following conditions must be met: 


    - SCR_EL3.HCE (bit 8) must be initialised to 0b1.



  For systems with a GICv5 interrupt controller to be used in v5 mode:



  - If the kernel is entered at EL1 and EL2 is present:



      - ICH_HFGRTR_EL2.ICC_PPI_ACTIVERn_EL1 (bit 20) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_PPI_PRIORITYRn_EL1 (bit 19) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_PPI_PENDRn_EL1 (bit 18) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_PPI_ENABLERn_EL1 (bit 17) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_PPI_HMRn_EL1 (bit 16) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_IAFFIDR_EL1 (bit 7) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_ICSR_EL1 (bit 6) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_PCR_EL1 (bit 5) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_HPPIR_EL1 (bit 4) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_HAPR_EL1 (bit 3) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_CR0_EL1 (bit 2) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_IDRn_EL1 (bit 1) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_APR_EL1 (bit 0) must be initialised to 0b1.



      - ICH_HFGWTR_EL2.ICC_PPI_ACTIVERn_EL1 (bit 20) must be initialised to 0b1.

      - ICH_HFGWTR_EL2.ICC_PPI_PRIORITYRn_EL1 (bit 19) must be initialised to 0b1.

      - ICH_HFGWTR_EL2.ICC_PPI_PENDRn_EL1 (bit 18) must be initialised to 0b1.

      - ICH_HFGWTR_EL2.ICC_PPI_ENABLERn_EL1 (bit 17) must be initialised to 0b1.

      - ICH_HFGWTR_EL2.ICC_ICSR_EL1 (bit 6) must be initialised to 0b1.

      - ICH_HFGWTR_EL2.ICC_PCR_EL1 (bit 5) must be initialised to 0b1.

      - ICH_HFGWTR_EL2.ICC_CR0_EL1 (bit 2) must be initialised to 0b1.

      - ICH_HFGWTR_EL2.ICC_APR_EL1 (bit 0) must be initialised to 0b1.



      - ICH_HFGITR_EL2.GICRCDNMIA (bit 10) must be initialised to 0b1.

      - ICH_HFGITR_EL2.GICRCDIA (bit 9) must be initialised to 0b1.

      - ICH_HFGITR_EL2.GICCDDI (bit 8) must be initialised to 0b1.

      - ICH_HFGITR_EL2.GICCDEOI (bit 7) must be initialised to 0b1.

      - ICH_HFGITR_EL2.GICCDHM (bit 6) must be initialised to 0b1.

      - ICH_HFGITR_EL2.GICCDRCFG (bit 5) must be initialised to 0b1.

      - ICH_HFGITR_EL2.GICCDPEND (bit 4) must be initialised to 0b1.

      - ICH_HFGITR_EL2.GICCDAFF (bit 3) must be initialised to 0b1.

      - ICH_HFGITR_EL2.GICCDPRI (bit 2) must be initialised to 0b1.

      - ICH_HFGITR_EL2.GICCDDIS (bit 1) must be initialised to 0b1.

      - ICH_HFGITR_EL2.GICCDEN (bit 0) must be initialised to 0b1.



  - The DT or ACPI tables must describe a GICv5 interrupt controller.



  For systems with a GICv3 interrupt controller to be used in v3 mode:

  - If EL3 is present:

Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5-iwb.yaml

0 → 100644
+78 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5-iwb.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: ARM Generic Interrupt Controller, version 5 Interrupt Wire Bridge (IWB)



maintainers:

  - Lorenzo Pieralisi <lpieralisi@kernel.org>

  - Marc Zyngier <maz@kernel.org>



description: |

  The GICv5 architecture defines the guidelines to implement GICv5

  compliant interrupt controllers for AArch64 systems.



  The GICv5 specification can be found at

  https://developer.arm.com/documentation/aes0070



  GICv5 has zero or more Interrupt Wire Bridges (IWB) that are responsible

  for translating wire signals into interrupt messages to the GICv5 ITS.



allOf:

  - $ref: /schemas/interrupt-controller.yaml#



properties:

  compatible:

    const: arm,gic-v5-iwb



  reg:

    items:

      - description: IWB control frame



  "#address-cells":

    const: 0



  "#interrupt-cells":

    description: |

      The 1st cell corresponds to the IWB wire.



      The 2nd cell is the flags, encoded as follows:

      bits[3:0] trigger type and level flags.



      1 = low-to-high edge triggered

      2 = high-to-low edge triggered

      4 = active high level-sensitive

      8 = active low level-sensitive



    const: 2



  interrupt-controller: true



  msi-parent:

    maxItems: 1



required:

  - compatible

  - reg

  - "#interrupt-cells"

  - interrupt-controller

  - msi-parent



additionalProperties: false



examples:

  - |

    interrupt-controller@2f000000 {

      compatible = "arm,gic-v5-iwb";

      reg = <0x2f000000 0x10000>;



      #address-cells = <0>;



      #interrupt-cells = <2>;

      interrupt-controller;



      msi-parent = <&its0 64>;

    };

...

Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml

0 → 100644
+267 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: ARM Generic Interrupt Controller, version 5



maintainers:

  - Lorenzo Pieralisi <lpieralisi@kernel.org>

  - Marc Zyngier <maz@kernel.org>



description: |

  The GICv5 architecture defines the guidelines to implement GICv5

  compliant interrupt controllers for AArch64 systems.



  The GICv5 specification can be found at

  https://developer.arm.com/documentation/aes0070



  The GICv5 architecture is composed of multiple components:

    - one or more IRS (Interrupt Routing Service)

    - zero or more ITS (Interrupt Translation Service)



  The architecture defines:

    - PE-Private Peripheral Interrupts (PPI)

    - Shared Peripheral Interrupts (SPI)

    - Logical Peripheral Interrupts (LPI)



allOf:

  - $ref: /schemas/interrupt-controller.yaml#



properties:

  compatible:

    const: arm,gic-v5



  "#address-cells":

    enum: [ 1, 2 ]



  "#size-cells":

    enum: [ 1, 2 ]



  ranges: true



  "#interrupt-cells":

    description: |

      The 1st cell corresponds to the INTID.Type field in the INTID; 1 for PPI,

      3 for SPI. LPI interrupts must not be described in the bindings since

      they are allocated dynamically by the software component managing them.



      The 2nd cell contains the interrupt INTID.ID field.



      The 3rd cell is the flags, encoded as follows:

      bits[3:0] trigger type and level flags.



        1 = low-to-high edge triggered

        2 = high-to-low edge triggered

        4 = active high level-sensitive

        8 = active low level-sensitive



    const: 3



  interrupt-controller: true



  interrupts:

    description:

      The VGIC maintenance interrupt.

    maxItems: 1



required:

  - compatible

  - "#address-cells"

  - "#size-cells"

  - ranges

  - "#interrupt-cells"

  - interrupt-controller



patternProperties:

  "^irs@[0-9a-f]+$":

    type: object

    description:

      GICv5 has one or more Interrupt Routing Services (IRS) that are

      responsible for handling IRQ state and routing.



    additionalProperties: false



    properties:

      compatible:

        const: arm,gic-v5-irs



      reg:

        minItems: 1

        items:

          - description: IRS config frames

          - description: IRS setlpi frames



      reg-names:

        description:

          Describe config and setlpi frames that are present.

          "ns-" stands for non-secure, "s-" for secure, "realm-" for realm

          and "el3-" for EL3.

        minItems: 1

        maxItems: 8

        items:

          enum: [ ns-config, s-config, realm-config, el3-config, ns-setlpi,

                  s-setlpi, realm-setlpi, el3-setlpi ]



      "#address-cells":

        enum: [ 1, 2 ]



      "#size-cells":

        enum: [ 1, 2 ]



      ranges: true



      dma-noncoherent:

        description:

          Present if the GIC IRS permits programming shareability and

          cacheability attributes but is connected to a non-coherent

          downstream interconnect.



      cpus:

        description:

          CPUs managed by the IRS.



      arm,iaffids:

        $ref: /schemas/types.yaml#/definitions/uint16-array

        description:

          Interrupt AFFinity ID (IAFFID) associated with the CPU whose

          CPU node phandle is at the same index in the cpus array.



    patternProperties:

      "^its@[0-9a-f]+$":

        type: object

        description:

          GICv5 has zero or more Interrupt Translation Services (ITS) that are

          used to route Message Signalled Interrupts (MSI) to the CPUs. Each

          ITS is connected to an IRS.

        additionalProperties: false



        properties:

          compatible:

            const: arm,gic-v5-its



          reg:

            items:

              - description: ITS config frames



          reg-names:

            description:

              Describe config frames that are present.

              "ns-" stands for non-secure, "s-" for secure, "realm-" for realm

              and "el3-" for EL3.

            minItems: 1

            maxItems: 4

            items:

              enum: [ ns-config, s-config, realm-config, el3-config ]



          "#address-cells":

            enum: [ 1, 2 ]



          "#size-cells":

            enum: [ 1, 2 ]



          ranges: true



          dma-noncoherent:

            description:

              Present if the GIC ITS permits programming shareability and

              cacheability attributes but is connected to a non-coherent

              downstream interconnect.



        patternProperties:

          "^msi-controller@[0-9a-f]+$":

            type: object

            description:

              GICv5 ITS has one or more translate register frames.

            additionalProperties: false



            properties:

              reg:

                items:

                  - description: ITS translate frames



              reg-names:

                description:

                  Describe translate frames that are present.

                  "ns-" stands for non-secure, "s-" for secure, "realm-" for realm

                  and "el3-" for EL3.

                minItems: 1

                maxItems: 4

                items:

                  enum: [ ns-translate, s-translate, realm-translate, el3-translate ]



              "#msi-cells":

                description:

                  The single msi-cell is the DeviceID of the device which will

                  generate the MSI.

                const: 1



              msi-controller: true



            required:

              - reg

              - reg-names

              - "#msi-cells"

              - msi-controller



        required:

          - compatible

          - reg

          - reg-names



    required:

      - compatible

      - reg

      - reg-names

      - cpus

      - arm,iaffids



additionalProperties: false



examples:

  - |

    interrupt-controller {

      compatible = "arm,gic-v5";



      #interrupt-cells = <3>;

      interrupt-controller;



      #address-cells = <1>;

      #size-cells = <1>;

      ranges;



      interrupts = <1 25 4>;



      irs@2f1a0000 {

        compatible = "arm,gic-v5-irs";

        reg = <0x2f1a0000 0x10000>;  // IRS_CONFIG_FRAME

        reg-names = "ns-config";



        #address-cells = <1>;

        #size-cells = <1>;

        ranges;



        cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;

        arm,iaffids = /bits/ 16 <0 1 2 3 4 5 6 7>;



        its@2f120000 {

          compatible = "arm,gic-v5-its";

          reg = <0x2f120000 0x10000>;   // ITS_CONFIG_FRAME

          reg-names = "ns-config";



          #address-cells = <1>;

          #size-cells = <1>;

          ranges;



          msi-controller@2f130000 {

            reg = <0x2f130000 0x10000>;   // ITS_TRANSLATE_FRAME

            reg-names = "ns-translate";



            #msi-cells = <1>;

            msi-controller;

          };

        };

      };

    };

...

Documentation/virt/kvm/api.rst

+12 −1
Original line number Diff line number Diff line
@@ -8622,7 +8622,7 @@ ENOSYS for the others. 
When enabled, KVM will exit to userspace with KVM_EXIT_SYSTEM_EVENT of

type KVM_SYSTEM_EVENT_SUSPEND to process the guest suspend request.



7.37 KVM_CAP_ARM_WRITABLE_IMP_ID_REGS

7.42 KVM_CAP_ARM_WRITABLE_IMP_ID_REGS

-------------------------------------



:Architectures: arm64
@@ -8651,6 +8651,17 @@ given VM. 
When this capability is enabled, KVM resets the VCPU when setting

MP_STATE_INIT_RECEIVED through IOCTL.  The original MP_STATE is preserved.



7.43 KVM_CAP_ARM_CACHEABLE_PFNMAP_SUPPORTED

-------------------------------------------



:Architectures: arm64

:Target: VM

:Parameters: None



This capability indicate to the userspace whether a PFNMAP memory region

can be safely mapped as cacheable. This relies on the presence of

force write back (FWB) feature support on the hardware.



8. Other capabilities.

======================

Documentation/virt/kvm/devices/arm-vgic-v3.rst

+75 −5
Original line number Diff line number Diff line
@@ -78,6 +78,8 @@ Groups: 
    -ENXIO   The group or attribute is unknown/unsupported for this device

             or hardware support is missing.

    -EFAULT  Invalid user pointer for attr->addr.

    -EBUSY   Attempt to write a register that is read-only after

             initialization

    =======  =============================================================
@@ -120,6 +122,15 @@ Groups: 
    Note that distributor fields are not banked, but return the same value

    regardless of the mpidr used to access the register.



    Userspace is allowed to write the following register fields prior to

    initialization of the VGIC:



      =====================

      GICD_IIDR.Revision

      GICD_TYPER2.nASSGIcap

      =====================





    GICD_IIDR.Revision is updated when the KVM implementation is changed in a

    way directly observable by the guest or userspace.  Userspace should read

    GICD_IIDR from KVM and write back the read value to confirm its expected
@@ -128,6 +139,12 @@ Groups: 
    behavior.





    GICD_TYPER2.nASSGIcap allows userspace to control the support of SGIs

    without an active state. At VGIC creation the field resets to the

    maximum capability of the system. Userspace is expected to read the field

    to determine the supported value(s) before writing to the field.





    The GICD_STATUSR and GICR_STATUSR registers are architecturally defined such

    that a write of a clear bit has no effect, whereas a write with a set bit

    clears that value.  To allow userspace to freely set the values of these two
@@ -202,16 +219,69 @@ Groups: 
    KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS accesses the CPU interface registers for the

    CPU specified by the mpidr field.



    CPU interface registers access is not implemented for AArch32 mode.

    Error -ENXIO is returned when accessed in AArch32 mode.

    The available registers are:



    ===============  ====================================================

    ICC_PMR_EL1

    ICC_BPR0_EL1

    ICC_AP0R0_EL1

    ICC_AP0R1_EL1    when the host implements at least 6 bits of priority

    ICC_AP0R2_EL1    when the host implements 7 bits of priority

    ICC_AP0R3_EL1    when the host implements 7 bits of priority

    ICC_AP1R0_EL1

    ICC_AP1R1_EL1    when the host implements at least 6 bits of priority

    ICC_AP1R2_EL1    when the host implements 7 bits of priority

    ICC_AP1R3_EL1    when the host implements 7 bits of priority

    ICC_BPR1_EL1

    ICC_CTLR_EL1

    ICC_SRE_EL1

    ICC_IGRPEN0_EL1

    ICC_IGRPEN1_EL1

    ===============  ====================================================



    When EL2 is available for the guest, these registers are also available:



    =============  ====================================================

    ICH_AP0R0_EL2

    ICH_AP0R1_EL2  when the host implements at least 6 bits of priority

    ICH_AP0R2_EL2  when the host implements 7 bits of priority

    ICH_AP0R3_EL2  when the host implements 7 bits of priority

    ICH_AP1R0_EL2

    ICH_AP1R1_EL2  when the host implements at least 6 bits of priority

    ICH_AP1R2_EL2  when the host implements 7 bits of priority

    ICH_AP1R3_EL2  when the host implements 7 bits of priority

    ICH_HCR_EL2

    ICC_SRE_EL2

    ICH_VTR_EL2

    ICH_VMCR_EL2

    ICH_LR0_EL2

    ICH_LR1_EL2

    ICH_LR2_EL2

    ICH_LR3_EL2

    ICH_LR4_EL2

    ICH_LR5_EL2

    ICH_LR6_EL2

    ICH_LR7_EL2

    ICH_LR8_EL2

    ICH_LR9_EL2

    ICH_LR10_EL2

    ICH_LR11_EL2

    ICH_LR12_EL2

    ICH_LR13_EL2

    ICH_LR14_EL2

    ICH_LR15_EL2

    =============  ====================================================



    CPU interface registers are only described using the AArch64

    encoding.



  Errors:



    =======  =====================================================

    -ENXIO   Getting or setting this register is not yet supported

    =======  =================================================

    -ENXIO   Getting or setting this register is not supported

    -EBUSY   VCPU is running

    -EINVAL  Invalid mpidr or register value supplied

    =======  =====================================================

    =======  =================================================





  KVM_DEV_ARM_VGIC_GRP_NR_IRQS