Commit 3154bddf authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvmarm-fixes-6.13-2' of... 

Merge tag 'kvmarm-fixes-6.13-2' of https://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD

KVM/arm64 fixes for 6.13, part #2

 - Fix confusion with implicitly-shifted MDCR_EL2 masks breaking
   SPE/TRBE initialization

 - Align nested page table walker with the intended memory attribute
   combining rules of the architecture

 - Prevent userspace from constraining the advertised ASID width,
   avoiding horrors of guest TLBIs not matching the intended context in
   hardware

 - Don't leak references on LPIs when insertion into the translation
   cache fails
parents fac04efc be7e6112

arch/arm64/include/asm/el2_setup.h

+2 −2
Original line number Diff line number Diff line
@@ -87,7 +87,7 @@ 
		      1 << PMSCR_EL2_PA_SHIFT)

	msr_s	SYS_PMSCR_EL2, x0		// addresses and physical counter

.Lskip_spe_el2_\@:

	mov	x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)

	mov	x0, #MDCR_EL2_E2PB_MASK

	orr	x2, x2, x0			// If we don't have VHE, then

						// use EL1&0 translation.
@@ -100,7 +100,7 @@ 
	and	x0, x0, TRBIDR_EL1_P

	cbnz	x0, .Lskip_trace_\@		// If TRBE is available at EL2



	mov	x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT)

	mov	x0, #MDCR_EL2_E2TB_MASK

	orr	x2, x2, x0			// allow the EL1&0 translation

						// to own it.

arch/arm64/kernel/hyp-stub.S

+2 −2
Original line number Diff line number Diff line
@@ -114,8 +114,8 @@ SYM_CODE_START_LOCAL(__finalise_el2) 


	// Use EL2 translations for SPE & TRBE and disable access from EL1

	mrs	x0, mdcr_el2

	bic	x0, x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)

	bic	x0, x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT)

	bic	x0, x0, #MDCR_EL2_E2PB_MASK

	bic	x0, x0, #MDCR_EL2_E2TB_MASK

	msr	mdcr_el2, x0



	// Transfer the MM state from EL1 to EL2

arch/arm64/kvm/at.c

+9 −2
Original line number Diff line number Diff line
@@ -739,8 +739,15 @@ static u64 compute_par_s12(struct kvm_vcpu *vcpu, u64 s1_par, 
			final_attr = s1_parattr;

			break;

		default:

			/* MemAttr[2]=0, Device from S2 */

			final_attr = s2_memattr & GENMASK(1,0) << 2;

			/*

			 * MemAttr[2]=0, Device from S2.

			 *

			 * FWB does not influence the way that stage 1

			 * memory types and attributes are combined

			 * with stage 2 Device type and attributes.

			 */

			final_attr = min(s2_memattr_to_attr(s2_memattr),

					 s1_parattr);

		}

	} else {

		/* Combination of R_HMNDG, R_TNHFM and R_GQFSF */

arch/arm64/kvm/hyp/nvhe/pkvm.c

+2 −2
Original line number Diff line number Diff line
@@ -126,7 +126,7 @@ static void pvm_init_traps_aa64dfr0(struct kvm_vcpu *vcpu) 
	/* Trap SPE */

	if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer), feature_ids)) {

		mdcr_set |= MDCR_EL2_TPMS;

		mdcr_clear |= MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT;

		mdcr_clear |= MDCR_EL2_E2PB_MASK;

	}



	/* Trap Trace Filter */
@@ -143,7 +143,7 @@ static void pvm_init_traps_aa64dfr0(struct kvm_vcpu *vcpu) 


	/* Trap External Trace */

	if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_ExtTrcBuff), feature_ids))

		mdcr_clear |= MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT;

		mdcr_clear |= MDCR_EL2_E2TB_MASK;



	vcpu->arch.mdcr_el2 |= mdcr_set;

	vcpu->arch.mdcr_el2 &= ~mdcr_clear;

arch/arm64/kvm/sys_regs.c

+2 −1
Original line number Diff line number Diff line
@@ -2618,7 +2618,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { 
	ID_WRITABLE(ID_AA64MMFR0_EL1, ~(ID_AA64MMFR0_EL1_RES0 |

					ID_AA64MMFR0_EL1_TGRAN4_2 |

					ID_AA64MMFR0_EL1_TGRAN64_2 |

					ID_AA64MMFR0_EL1_TGRAN16_2)),

					ID_AA64MMFR0_EL1_TGRAN16_2 |

					ID_AA64MMFR0_EL1_ASIDBITS)),

	ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 |

					ID_AA64MMFR1_EL1_HCX |

					ID_AA64MMFR1_EL1_TWED |