Commit 3158223e authored by Eric Bernstein's avatar Eric Bernstein Committed by Alex Deucher
Browse files

drm/amd/display: Refactor otg_blank sequence 



Also rename otg_blank to blank_pixel_data.

Signed-off-by: default avatarEric Bernstein <eric.bernstein@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8e357610

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+3 −3
Original line number Diff line number Diff line
@@ -1233,7 +1233,7 @@ static void program_scaler(const struct dc *dc, 
		&pipe_ctx->plane_res.scl_data);

}



static enum dc_status dce110_prog_pixclk_crtc_otg(

static enum dc_status dce110_enable_stream_timing(

		struct pipe_ctx *pipe_ctx,

		struct dc_state *context,

		struct dc *dc)
@@ -1299,7 +1299,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( 
			pipe_ctx[pipe_ctx->pipe_idx];



	/*  */

	dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc);

	dc->hwss.enable_stream_timing(pipe_ctx, context, dc);



	/* FPGA does not program backend */

	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
@@ -3041,7 +3041,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { 
	.get_position = get_position,

	.set_static_screen_control = set_static_screen_control,

	.reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,

	.prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg,

	.enable_stream_timing = dce110_enable_stream_timing,

	.setup_stereo = NULL,

	.set_avmute = dce110_set_avmute,

	.wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+18 −17
Original line number Diff line number Diff line
@@ -593,7 +593,7 @@ static void false_optc_underflow_wa( 
		tg->funcs->clear_optc_underflow(tg);

}



static enum dc_status dcn10_prog_pixclk_crtc_otg(

static enum dc_status dcn10_enable_stream_timing(

		struct pipe_ctx *pipe_ctx,

		struct dc_state *context,

		struct dc *dc)
@@ -1950,9 +1950,9 @@ static void update_dchubp_dpp( 
		hubp->funcs->set_blank(hubp, false);

}



static void dcn10_otg_blank(

static void dcn10_blank_pixel_data(

		struct dc *dc,

		struct stream_resource stream_res,

		struct stream_resource *stream_res,

		struct dc_stream_state *stream,

		bool blank)

{
@@ -1963,21 +1963,21 @@ static void dcn10_otg_blank( 
	color_space = stream->output_color_space;

	color_space_to_black_color(dc, color_space, &black_color);



	if (stream_res.tg->funcs->set_blank_color)

		stream_res.tg->funcs->set_blank_color(

				stream_res.tg,

	if (stream_res->tg->funcs->set_blank_color)

		stream_res->tg->funcs->set_blank_color(

				stream_res->tg,

				&black_color);



	if (!blank) {

		if (stream_res.tg->funcs->set_blank)

			stream_res.tg->funcs->set_blank(stream_res.tg, blank);

		if (stream_res.abm)

			stream_res.abm->funcs->set_abm_level(stream_res.abm, stream->abm_level);

		if (stream_res->tg->funcs->set_blank)

			stream_res->tg->funcs->set_blank(stream_res->tg, blank);

		if (stream_res->abm)

			stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);

	} else if (blank) {

		if (stream_res.abm)

			stream_res.abm->funcs->set_abm_immediate_disable(stream_res.abm);

		if (stream_res.tg->funcs->set_blank)

			stream_res.tg->funcs->set_blank(stream_res.tg, blank);

		if (stream_res->abm)

			stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);

		if (stream_res->tg->funcs->set_blank)

			stream_res->tg->funcs->set_blank(stream_res->tg, blank);

	}

}
@@ -2016,7 +2016,7 @@ static void program_all_pipe_in_tree( 
		pipe_ctx->stream_res.tg->funcs->program_global_sync(

				pipe_ctx->stream_res.tg);



		dcn10_otg_blank(dc, pipe_ctx->stream_res,

		dc->hwss.blank_pixel_data(dc, &pipe_ctx->stream_res,

				pipe_ctx->stream, blank);

	}
@@ -2136,7 +2136,7 @@ static void dcn10_apply_ctx_for_surface( 


	if (num_planes == 0) {

		/* OTG blank before remove all front end */

		dcn10_otg_blank(dc, top_pipe_to_program->stream_res, top_pipe_to_program->stream, true);

		dc->hwss.blank_pixel_data(dc, &top_pipe_to_program->stream_res, top_pipe_to_program->stream, true);

	}



	/* Disconnect unused mpcc */
@@ -2679,10 +2679,11 @@ static const struct hw_sequencer_funcs dcn10_funcs = { 
	.blank_stream = dce110_blank_stream,

	.enable_display_power_gating = dcn10_dummy_display_power_gating,

	.disable_plane = dcn10_disable_plane,

	.blank_pixel_data = dcn10_blank_pixel_data,

	.pipe_control_lock = dcn10_pipe_control_lock,

	.set_bandwidth = dcn10_set_bandwidth,

	.reset_hw_ctx_wrap = reset_hw_ctx_wrap,

	.prog_pixclk_crtc_otg = dcn10_prog_pixclk_crtc_otg,

	.enable_stream_timing = dcn10_enable_stream_timing,

	.set_drr = set_drr,

	.get_position = get_position,

	.set_static_screen_control = set_static_screen_control,

drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h

+7 −1
Original line number Diff line number Diff line
@@ -65,6 +65,7 @@ struct dchub_init_data; 
struct dc_static_screen_events;

struct resource_pool;

struct resource_context;

struct stream_resource;



struct hw_sequencer_funcs {
@@ -162,6 +163,11 @@ struct hw_sequencer_funcs { 
				struct dc *dc,

				struct pipe_ctx *pipe,

				bool lock);

	void (*blank_pixel_data)(

			struct dc *dc,

			struct stream_resource *stream_res,

			struct dc_stream_state *stream,

			bool blank);



	void (*set_bandwidth)(

			struct dc *dc,
@@ -177,7 +183,7 @@ struct hw_sequencer_funcs { 
	void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,

			int num_pipes, const struct dc_static_screen_events *events);



	enum dc_status (*prog_pixclk_crtc_otg)(

	enum dc_status (*enable_stream_timing)(

			struct pipe_ctx *pipe_ctx,

			struct dc_state *context,

			struct dc *dc);