Unverified Commit 3178d58e authored by Herve Codina's avatar Herve Codina Committed by Mark Brown
Browse files

soc: fsl: cpm1: Add support for QMC 



The QMC (QUICC Multichannel Controller) emulates up to 64
channels within one serial controller using the same TDM
physical interface routed from the TSA.

It is available in some	PowerQUICC SoC such as the
MPC885 or MPC866.

It is also available on some Quicc Engine SoCs.
This current version support CPM1 SoCs only and some
enhancement are needed to support Quicc Engine SoCs.

Signed-off-by: default avatarHerve Codina <herve.codina@bootlin.com>
Acked-by: default avatarLi Yang <leoyang.li@nxp.com>
Reviewed-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20230217145645.1768659-7-herve.codina@bootlin.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent a9b12132

drivers/soc/fsl/qe/Kconfig

+12 −0
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@@ -44,6 +44,18 @@ config CPM_TSA 
	  This option enables support for this

	  controller



config CPM_QMC

	tristate "CPM QMC support"

	depends on OF && HAS_IOMEM

	depends on CPM1 || (SOC_FSL && COMPILE_TEST)

	depends on CPM_TSA

	help

	  Freescale CPM QUICC Multichannel Controller

	  (QMC)



	  This option enables support for this

	  controller



config QE_TDM

	bool

	default y if FSL_UCC_HDLC

drivers/soc/fsl/qe/Makefile

+1 −0
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@@ -5,6 +5,7 @@ 
obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o

obj-$(CONFIG_CPM)	+= qe_common.o

obj-$(CONFIG_CPM_TSA)	+= tsa.o

obj-$(CONFIG_CPM_QMC)	+= qmc.o

obj-$(CONFIG_UCC)	+= ucc.o

obj-$(CONFIG_UCC_SLOW)	+= ucc_slow.o

obj-$(CONFIG_UCC_FAST)	+= ucc_fast.o

drivers/soc/fsl/qe/qmc.c

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+1533 −0

File added.

Preview size limit exceeded, changes collapsed.

include/soc/fsl/qe/qmc.h

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/* SPDX-License-Identifier: GPL-2.0-or-later */

/*

 * QMC management

 *

 * Copyright 2022 CS GROUP France

 *

 * Author: Herve Codina <herve.codina@bootlin.com>

 */

#ifndef __SOC_FSL_QMC_H__

#define __SOC_FSL_QMC_H__



#include <linux/types.h>



struct device_node;

struct device;

struct qmc_chan;



struct qmc_chan *qmc_chan_get_byphandle(struct device_node *np, const char *phandle_name);

void qmc_chan_put(struct qmc_chan *chan);

struct qmc_chan *devm_qmc_chan_get_byphandle(struct device *dev, struct device_node *np,

					     const char *phandle_name);



enum qmc_mode {

	QMC_TRANSPARENT,

	QMC_HDLC,

};



struct qmc_chan_info {

	enum qmc_mode mode;

	unsigned long rx_fs_rate;

	unsigned long rx_bit_rate;

	u8 nb_rx_ts;

	unsigned long tx_fs_rate;

	unsigned long tx_bit_rate;

	u8 nb_tx_ts;

};



int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info);



struct qmc_chan_param {

	enum qmc_mode mode;

	union {

		struct {

			u16 max_rx_buf_size;

			u16 max_rx_frame_size;

			bool is_crc32;

		} hdlc;

		struct {

			u16 max_rx_buf_size;

		} transp;

	};

};



int qmc_chan_set_param(struct qmc_chan *chan, const struct qmc_chan_param *param);



int qmc_chan_write_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,

			  void (*complete)(void *context), void *context);



int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,

			 void (*complete)(void *context, size_t length),

			 void *context);



#define QMC_CHAN_READ  (1<<0)

#define QMC_CHAN_WRITE (1<<1)

#define QMC_CHAN_ALL   (QMC_CHAN_READ | QMC_CHAN_WRITE)



int qmc_chan_start(struct qmc_chan *chan, int direction);

int qmc_chan_stop(struct qmc_chan *chan, int direction);

int qmc_chan_reset(struct qmc_chan *chan, int direction);



#endif /* __SOC_FSL_QMC_H__ */