Unverified Commit 317bbe16 authored by Vadim Pasternak's avatar Vadim Pasternak Committed by Ilpo Järvinen
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platform: mellanox: mlx-platform: Add support for new Nvidia system 



Add support for SN5640 and SN5610 Nvidia switches:
- SN5610 is a 51.2Tbps switch based on Nvidia SPC-4 ASIC equipped with 64
  OSFP ports supporting 2.5Gbps - 400Gbps speeds.
- SN5640 is a 51.2Tbps switch based on Nvidia SPC-5 ASIC equipped with 64
  OSFP ports supporting 10Gbps - 800Gbps speeds.

Both equipped with:
- Air-cooled with 4 + 1 redundant fan units.
- 2 + 2 redundant 2000W PSUs.
- System management board based on AMD CPU with secure-boot support.

Reviewed-by: default avatarOleksandr Shamray <oleksandrs@nvidia.com>
Signed-off-by: default avatarVadim Pasternak <vadimp@nvidia.com>
Link: https://lore.kernel.org/r/20250421092051.7687-5-vadimp@nvidia.com


Reviewed-by: default avatarIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: default avatarIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
parent f48cf5ee

drivers/platform/mellanox/mlx-platform.c

+96 −0
Original line number Diff line number Diff line
@@ -3000,6 +3000,59 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_l1_switch_data = { 
	.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT,

};



/* Platform hotplug for 800G systems family data  */

static struct mlxreg_core_item mlxplat_mlxcpld_ng800_hi171_items[] = {

	{

		.data = mlxplat_mlxcpld_ext_psu_items_data,

		.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,

		.reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,

		.mask = MLXPLAT_CPLD_PSU_EXT_MASK,

		.capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,

		.count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data),

		.inversed = 1,

		.health = false,

	},

	{

		.data = mlxplat_mlxcpld_modular_pwr_items_data,

		.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,

		.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,

		.mask = MLXPLAT_CPLD_PWR_EXT_MASK,

		.capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,

		.count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data),

		.inversed = 0,

		.health = false,

	},

	{

		.data = mlxplat_mlxcpld_xdr_fan_items_data,

		.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,

		.reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,

		.mask = MLXPLAT_CPLD_FAN_XDR_MASK,

		.capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,

		.count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_items_data),

		.inversed = 1,

		.health = false,

	},

	{

		.data = mlxplat_mlxcpld_default_asic_items_data,

		.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,

		.reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,

		.mask = MLXPLAT_CPLD_ASIC_MASK,

		.count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),

		.inversed = 0,

		.health = true,

	},

};



static

struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_hi171_data = {

	.items = mlxplat_mlxcpld_ng800_hi171_items,

	.count = ARRAY_SIZE(mlxplat_mlxcpld_ng800_hi171_items),

	.cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,

	.mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX,

	.cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,

	.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2,

};



/* Platform led default data */

static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = {

	{
@@ -4486,6 +4539,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { 
		.mask = GENMASK(7, 0) & ~BIT(4),

		.mode = 0644,

	},

	{

		.label = "shutdown_unlock",

		.reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,

		.mask = GENMASK(7, 0) & ~BIT(5),

		.mode = 0644,

	},

	{

		.label = "erot1_ap_reset",

		.reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
@@ -7312,6 +7371,29 @@ static int __init mlxplat_dmi_smart_switch_matched(const struct dmi_system_id *d 
	return mlxplat_register_platform_device();

}



static int __init mlxplat_dmi_ng400_hi171_matched(const struct dmi_system_id *dmi)

{

	unsigned int i;



	mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;

	mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data);

	mlxplat_mux_data = mlxplat_ng800_mux_data;

	mlxplat_hotplug = &mlxplat_mlxcpld_ng800_hi171_data;

	mlxplat_hotplug->deferred_nr =

		mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];

	mlxplat_led = &mlxplat_default_ng_led_data;

	mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;

	mlxplat_fan = &mlxplat_xdr_fan_data;



	for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++)

		mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type3[i];



	mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;

	mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400;



	return mlxplat_register_platform_device();

}



static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {

	{

		.callback = mlxplat_dmi_default_wc_matched,
@@ -7412,6 +7494,20 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { 
			DMI_MATCH(DMI_BOARD_NAME, "VMOD0019"),

		},

	},

	{

		.callback = mlxplat_dmi_ng400_hi171_matched,

		.matches = {

			DMI_MATCH(DMI_BOARD_NAME, "VMOD0022"),

			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI171"),

		},

	},

	{

		.callback = mlxplat_dmi_ng400_hi171_matched,

		.matches = {

			DMI_MATCH(DMI_BOARD_NAME, "VMOD0022"),

			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI172"),

		},

	},

	{

		.callback = mlxplat_dmi_msn274x_matched,

		.matches = {