Commit 320e7efc authored by André Draszik's avatar André Draszik Committed by Krzysztof Kozlowski
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clk: samsung: exynos850: fix a comment 



The code below the updated comment is for CMU_CPUCL1, not CMU_CPUCL0.

Fixes: dedf8734 ("clk: samsung: exynos850: Add CMU_CPUCL0 and CMU_CPUCL1")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarAndré Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20250603-samsung-clk-fixes-v1-3-49daf1ff4592@linaro.org


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent ca243e65

drivers/clk/samsung/clk-exynos850.c

+1 −1
Original line number Diff line number Diff line
@@ -1360,7 +1360,7 @@ static const unsigned long cpucl1_clk_regs[] __initconst = { 
	CLK_CON_GAT_GATE_CLK_CPUCL1_CPU,

};



/* List of parent clocks for Muxes in CMU_CPUCL0 */

/* List of parent clocks for Muxes in CMU_CPUCL1 */

PNAME(mout_pll_cpucl1_p)		 = { "oscclk", "fout_cpucl1_pll" };

PNAME(mout_cpucl1_switch_user_p)	 = { "oscclk", "dout_cpucl1_switch" };

PNAME(mout_cpucl1_dbg_user_p)		 = { "oscclk", "dout_cpucl1_dbg" };