Commit 32104b29 authored by Kyle McMartin's avatar Kyle McMartin Committed by Matthew Wilcox
Browse files

[PARISC] PA7200 also supports prefetch for read 



It seems PA7200 processors also suppress traps on loads to
%r0. This means we can prefetch for read on these cpus. Of course,
we can't support prefetch for write, since that requires
LOAD DOUBLEWORD which was added with PA2.0

Signed-off-by: default avatarKyle McMartin <kyle@parisc-linux.org>
parent 4068d93c

arch/parisc/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -127,7 +127,7 @@ config PA11 


config PREFETCH

	def_bool y

	depends on PA8X00

	depends on PA8X00 || PA7200



config 64BIT

	bool "64-bit kernel"

include/asm-parisc/prefetch.h

+3 −0
Original line number Diff line number Diff line
@@ -24,11 +24,14 @@ extern inline void prefetch(const void *addr) 
	__asm__("ldw 0(%0), %%r0" : : "r" (addr));

}



/* LDD is a PA2.0 addition. */

#ifdef CONFIG_PA20

#define ARCH_HAS_PREFETCHW

extern inline void prefetchw(const void *addr)

{

	__asm__("ldd 0(%0), %%r0" : : "r" (addr));

}

#endif /* CONFIG_PA20 */



#endif /* CONFIG_PREFETCH */

#endif /* __ASSEMBLY__ */