Commit 3235704c authored by Ian Rogers's avatar Ian Rogers Committed by Namhyung Kim
Browse files

perf vendor events: Update ivytown metrics add event counter information 

Add counter information necessary for optimizing event grouping the
perf tool.

The most recent RFC patch set using this information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/

The information was added in:
https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4765e1
and later patches.

The TMA 4.8 information was updated in:
https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9a5736



Co-authored-by: default avatarWeilin Wang <weilin.wang@intel.com>
Co-authored-by: default avatarCaleb Biggers <caleb.biggers@intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: default avatarNamhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-20-irogers@google.com
parent 238a2117

tools/perf/pmu-events/arch/x86/ivytown/cache.json

+118 −0

File changed.

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tools/perf/pmu-events/arch/x86/ivytown/counter.json

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+52 −0
Original line number Diff line number Diff line 
[

    {

        "Unit": "core",

        "CountersNumFixed": "3",

        "CountersNumGeneric": "4"

    },

    {

        "Unit": "CBOX",

        "CountersNumFixed": "0",

        "CountersNumGeneric": "4"

    },

    {

        "Unit": "HA",

        "CountersNumFixed": "0",

        "CountersNumGeneric": "4"

    },

    {

        "Unit": "iMC",

        "CountersNumFixed": "0",

        "CountersNumGeneric": "4"

    },

    {

        "Unit": "IRP",

        "CountersNumFixed": "0",

        "CountersNumGeneric": "2"

    },

    {

        "Unit": "PCU",

        "CountersNumFixed": "0",

        "CountersNumGeneric": "4"

    },

    {

        "Unit": "QPI",

        "CountersNumFixed": "0",

        "CountersNumGeneric": "4"

    },

    {

        "Unit": "R2PCIe",

        "CountersNumFixed": "0",

        "CountersNumGeneric": "4"

    },

    {

        "Unit": "R3QPI",

        "CountersNumFixed": "0",

        "CountersNumGeneric": "3"

    },

    {

        "Unit": "UBOX",

        "CountersNumFixed": "0",

        "CountersNumGeneric": "2"

    }

]
 
 No newline at end of file

tools/perf/pmu-events/arch/x86/ivytown/floating-point.json

+17 −0
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Cycles with any input/output SSE or FP assist",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.ANY",
@@ -10,6 +11,7 @@ 
    },

    {

        "BriefDescription": "Number of SIMD FP assists due to input values",

        "Counter": "0,1,2,3",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.SIMD_INPUT",

        "PublicDescription": "Number of SIMD FP assists due to input values.",
@@ -18,6 +20,7 @@ 
    },

    {

        "BriefDescription": "Number of SIMD FP assists due to Output values",

        "Counter": "0,1,2,3",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.SIMD_OUTPUT",

        "PublicDescription": "Number of SIMD FP assists due to output values.",
@@ -26,6 +29,7 @@ 
    },

    {

        "BriefDescription": "Number of X87 assists due to input value.",

        "Counter": "0,1,2,3",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.X87_INPUT",

        "PublicDescription": "Number of X87 FP assists due to input values.",
@@ -34,6 +38,7 @@ 
    },

    {

        "BriefDescription": "Number of X87 assists due to output value.",

        "Counter": "0,1,2,3",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.X87_OUTPUT",

        "PublicDescription": "Number of X87 FP assists due to output values.",
@@ -42,6 +47,7 @@ 
    },

    {

        "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle",

        "Counter": "0,1,2,3",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",

        "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
@@ -50,6 +56,7 @@ 
    },

    {

        "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle",

        "Counter": "0,1,2,3",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",

        "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
@@ -58,6 +65,7 @@ 
    },

    {

        "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle",

        "Counter": "0,1,2,3",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",

        "PublicDescription": "Counts number of SSE* or AVX-128 double precision FP scalar uops executed.",
@@ -66,6 +74,7 @@ 
    },

    {

        "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle",

        "Counter": "0,1,2,3",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",

        "PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
@@ -74,6 +83,7 @@ 
    },

    {

        "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s",

        "Counter": "0,1,2,3",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.X87",

        "PublicDescription": "Counts number of X87 uops executed.",
@@ -82,6 +92,7 @@ 
    },

    {

        "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",

        "Counter": "0,1,2,3",

        "EventCode": "0x58",

        "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",

        "SampleAfterValue": "1000003",
@@ -89,6 +100,7 @@ 
    },

    {

        "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",

        "Counter": "0,1,2,3",

        "EventCode": "0x58",

        "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",

        "SampleAfterValue": "1000003",
@@ -96,6 +108,7 @@ 
    },

    {

        "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",

        "Counter": "0,1,2,3",

        "EventCode": "0xC1",

        "EventName": "OTHER_ASSISTS.AVX_STORE",

        "PublicDescription": "Number of assists associated with 256-bit AVX store operations.",
@@ -104,6 +117,7 @@ 
    },

    {

        "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

        "Counter": "0,1,2,3",

        "EventCode": "0xC1",

        "EventName": "OTHER_ASSISTS.AVX_TO_SSE",

        "SampleAfterValue": "100003",
@@ -111,6 +125,7 @@ 
    },

    {

        "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

        "Counter": "0,1,2,3",

        "EventCode": "0xC1",

        "EventName": "OTHER_ASSISTS.SSE_TO_AVX",

        "SampleAfterValue": "100003",
@@ -118,6 +133,7 @@ 
    },

    {

        "BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle",

        "Counter": "0,1,2,3",

        "EventCode": "0x11",

        "EventName": "SIMD_FP_256.PACKED_DOUBLE",

        "PublicDescription": "Counts 256-bit packed double-precision floating-point instructions.",
@@ -126,6 +142,7 @@ 
    },

    {

        "BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",

        "Counter": "0,1,2,3",

        "EventCode": "0x11",

        "EventName": "SIMD_FP_256.PACKED_SINGLE",

        "PublicDescription": "Counts 256-bit packed single-precision floating-point instructions.",

tools/perf/pmu-events/arch/x86/ivytown/frontend.json

+30 −0
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",

        "Counter": "0,1,2,3",

        "EventCode": "0xE6",

        "EventName": "BACLEARS.ANY",

        "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
@@ -9,6 +10,7 @@ 
    },

    {

        "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",

        "Counter": "0,1,2,3",

        "EventCode": "0xAB",

        "EventName": "DSB2MITE_SWITCHES.COUNT",

        "PublicDescription": "Number of DSB to MITE switches.",
@@ -17,6 +19,7 @@ 
    },

    {

        "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",

        "Counter": "0,1,2,3",

        "EventCode": "0xAB",

        "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",

        "PublicDescription": "Cycles DSB to MITE switches caused delay.",
@@ -25,6 +28,7 @@ 
    },

    {

        "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",

        "Counter": "0,1,2,3",

        "EventCode": "0xAC",

        "EventName": "DSB_FILL.EXCEED_DSB_LINES",

        "PublicDescription": "DSB Fill encountered > 3 DSB lines.",
@@ -33,6 +37,7 @@ 
    },

    {

        "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",

        "Counter": "0,1,2,3",

        "EventCode": "0x80",

        "EventName": "ICACHE.HIT",

        "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
@@ -41,6 +46,7 @@ 
    },

    {

        "BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss",

        "Counter": "0,1,2,3",

        "EventCode": "0x80",

        "EventName": "ICACHE.IFETCH_STALL",

        "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.",
@@ -49,6 +55,7 @@ 
    },

    {

        "BriefDescription": "Instruction cache, streaming buffer and victim cache misses",

        "Counter": "0,1,2,3",

        "EventCode": "0x80",

        "EventName": "ICACHE.MISSES",

        "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.",
@@ -57,6 +64,7 @@ 
    },

    {

        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",

        "Counter": "0,1,2,3",

        "CounterMask": "4",

        "EventCode": "0x79",

        "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -66,6 +74,7 @@ 
    },

    {

        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -75,6 +84,7 @@ 
    },

    {

        "BriefDescription": "Cycles MITE is delivering 4 Uops",

        "Counter": "0,1,2,3",

        "CounterMask": "4",

        "EventCode": "0x79",

        "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -84,6 +94,7 @@ 
    },

    {

        "BriefDescription": "Cycles MITE is delivering any Uop",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -93,6 +104,7 @@ 
    },

    {

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.DSB_CYCLES",
@@ -102,6 +114,7 @@ 
    },

    {

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

        "Counter": "0,1,2,3",

        "EventCode": "0x79",

        "EventName": "IDQ.DSB_UOPS",

        "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
@@ -110,6 +123,7 @@ 
    },

    {

        "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",

        "Counter": "0,1,2,3",

        "EventCode": "0x79",

        "EventName": "IDQ.EMPTY",

        "PublicDescription": "Counts cycles the IDQ is empty.",
@@ -118,6 +132,7 @@ 
    },

    {

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

        "Counter": "0,1,2,3",

        "EventCode": "0x79",

        "EventName": "IDQ.MITE_ALL_UOPS",

        "PublicDescription": "Number of uops delivered to IDQ from any path.",
@@ -126,6 +141,7 @@ 
    },

    {

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.MITE_CYCLES",
@@ -135,6 +151,7 @@ 
    },

    {

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

        "Counter": "0,1,2,3",

        "EventCode": "0x79",

        "EventName": "IDQ.MITE_UOPS",

        "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
@@ -143,6 +160,7 @@ 
    },

    {

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_CYCLES",
@@ -152,6 +170,7 @@ 
    },

    {

        "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_DSB_CYCLES",
@@ -161,6 +180,7 @@ 
    },

    {

        "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EdgeDetect": "1",

        "EventCode": "0x79",
@@ -171,6 +191,7 @@ 
    },

    {

        "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",

        "Counter": "0,1,2,3",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_DSB_UOPS",

        "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
@@ -179,6 +200,7 @@ 
    },

    {

        "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",

        "Counter": "0,1,2,3",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_MITE_UOPS",

        "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
@@ -187,6 +209,7 @@ 
    },

    {

        "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EdgeDetect": "1",

        "EventCode": "0x79",
@@ -197,6 +220,7 @@ 
    },

    {

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",

        "Counter": "0,1,2,3",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_UOPS",

        "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.",
@@ -205,6 +229,7 @@ 
    },

    {

        "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",

        "Counter": "0,1,2,3",

        "EventCode": "0x9C",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",

        "PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.",
@@ -213,6 +238,7 @@ 
    },

    {

        "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",

        "Counter": "0,1,2,3",

        "CounterMask": "4",

        "EventCode": "0x9C",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -221,6 +247,7 @@ 
    },

    {

        "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0x9C",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -230,6 +257,7 @@ 
    },

    {

        "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",

        "Counter": "0,1,2,3",

        "CounterMask": "3",

        "EventCode": "0x9C",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -238,6 +266,7 @@ 
    },

    {

        "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",

        "Counter": "0,1,2,3",

        "CounterMask": "2",

        "EventCode": "0x9C",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -246,6 +275,7 @@ 
    },

    {

        "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0x9C",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",

tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json

+37 −31

File changed.

Preview size limit exceeded, changes collapsed.