Commit 3257e55d authored by Animesh Manna's avatar Animesh Manna
Browse files

drm/i915/panelreplay: enable/disable panel replay 



TRANS_DP2_CTL register is programmed to enable panel replay from source
and sink is enabled through panel replay dpcd configuration address.

Bspec: 1407940617

v1: Initial version.
v2:
- Use pr_* flags instead psr_* flags. [Jouni]
- Remove intel_dp_is_edp check as edp1.5 also has panel replay. [Jouni]

v3: Cover letter updated and selective fetch condition check is added
before updating its bit in PSR2_MAN_TRK_CTL register. [Jouni]

v4: Selective fetch related PSR2_MAN_TRK_CTL programmming dropped. [Jouni]

v5: Added PSR2_MAN_TRK_CTL programming as needed for Continuous Full
Frame (CFF) update.

v6: Rebased on latest.

Note: Initial plan is to enable panel replay in  full-screen live active
frame update mode. In a incremental approach panel replay will be enabled
in selctive update mode if there is any gap in curent implementation.

Cc: Jouni Högander <jouni.hogander@intel.com>
Cc: Arun R Murthy <arun.r.murthy@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarArun R Murthy <arun.r.murthy@intel.com>
Signed-off-by: default avatarAnimesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231108072303.3414118-6-animesh.manna@intel.com
parent cceeaa31

drivers/gpu/drm/i915/display/intel_ddi.c

+6 −1
Original line number Diff line number Diff line
@@ -2800,10 +2800,15 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 
				    const struct drm_connector_state *conn_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);



	if (HAS_DP20(dev_priv))

	if (HAS_DP20(dev_priv)) {

		intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),

					    crtc_state);

		if (crtc_state->has_panel_replay)

			drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,

					   DP_PANEL_REPLAY_ENABLE);

	}



	if (DISPLAY_VER(dev_priv) >= 14)

		mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_display_types.h

+1 −0
Original line number Diff line number Diff line
@@ -1711,6 +1711,7 @@ struct intel_psr { 
	u16 su_y_granularity;

	bool source_panel_replay_support;

	bool sink_panel_replay_support;

	bool panel_replay_enabled;

	u32 dc3co_exitline;

	u32 dc3co_exit_delay;

	struct delayed_work dc3co_work;

drivers/gpu/drm/i915/display/intel_psr.c

+48 −15
Original line number Diff line number Diff line
@@ -609,8 +609,11 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp) 
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	u8 dpcd_val = DP_PSR_ENABLE;



	/* Enable ALPM at sink for psr2 */

	if (intel_dp->psr.panel_replay_enabled)

		return;



	if (intel_dp->psr.psr2_enabled) {

		/* Enable ALPM at sink for psr2 */

		drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,

				   DP_ALPM_ENABLE |

				   DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
@@ -783,6 +786,17 @@ static u8 frames_before_su_entry(struct intel_dp *intel_dp) 
	return frames_before_su_entry;

}



static void dg2_activate_panel_replay(struct intel_dp *intel_dp)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);



	intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),

		     0, ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME);



	intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,

		     TRANS_DP2_PANEL_REPLAY_ENABLE);

}



static void hsw_activate_psr2(struct intel_dp *intel_dp)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1379,18 +1393,23 @@ void intel_psr_get_config(struct intel_encoder *encoder, 
		return;



	intel_dp = &dig_port->dp;

	if (!CAN_PSR(intel_dp))

	if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp)))

		return;



	mutex_lock(&intel_dp->psr.lock);

	if (!intel_dp->psr.enabled)

		goto unlock;



	if (intel_dp->psr.panel_replay_enabled) {

		pipe_config->has_panel_replay = true;

	} else {

		/*

		 * Not possible to read EDP_PSR/PSR2_CTL registers as it is

		 * enabled/disabled because of frontbuffer tracking and others.

		 */

		pipe_config->has_psr = true;

	}



	pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;

	pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
@@ -1427,8 +1446,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp) 


	lockdep_assert_held(&intel_dp->psr.lock);



	/* psr1 and psr2 are mutually exclusive.*/

	if (intel_dp->psr.psr2_enabled)

	/* psr1, psr2 and panel-replay are mutually exclusive.*/

	if (intel_dp->psr.panel_replay_enabled)

		dg2_activate_panel_replay(intel_dp);

	else if (intel_dp->psr.psr2_enabled)

		hsw_activate_psr2(intel_dp);

	else

		hsw_activate_psr1(intel_dp);
@@ -1606,6 +1627,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, 
	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);



	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;

	intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;

	intel_dp->psr.busy_frontbuffer_bits = 0;

	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;

	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
@@ -1621,8 +1643,12 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, 
	if (!psr_interrupt_error_check(intel_dp))

		return;



	if (intel_dp->psr.panel_replay_enabled)

		drm_dbg_kms(&dev_priv->drm, "Enabling Panel Replay\n");

	else

		drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",

			    intel_dp->psr.psr2_enabled ? "2" : "1");



	intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc);

	intel_snps_phy_update_psr_power_state(dev_priv, phy, true);

	intel_psr_enable_sink(intel_dp);
@@ -1651,7 +1677,10 @@ static void intel_psr_exit(struct intel_dp *intel_dp) 
		return;

	}



	if (intel_dp->psr.psr2_enabled) {

	if (intel_dp->psr.panel_replay_enabled) {

		intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder),

			     TRANS_DP2_PANEL_REPLAY_ENABLE, 0);

	} else if (intel_dp->psr.psr2_enabled) {

		tgl_disallow_dc3co_on_psr2_exit(intel_dp);



		val = intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder),
@@ -1700,6 +1729,9 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) 
	if (!intel_dp->psr.enabled)

		return;



	if (intel_dp->psr.panel_replay_enabled)

		drm_dbg_kms(&dev_priv->drm, "Disabling Panel Replay\n");

	else

		drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",

			    intel_dp->psr.psr2_enabled ? "2" : "1");
@@ -1734,6 +1766,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) 
		drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0);



	intel_dp->psr.enabled = false;

	intel_dp->psr.panel_replay_enabled = false;

	intel_dp->psr.psr2_enabled = false;

	intel_dp->psr.psr2_sel_fetch_enabled = false;

	intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
@@ -2305,7 +2338,7 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state, 
		intel_atomic_get_new_crtc_state(state, crtc);

	struct intel_encoder *encoder;



	if (!crtc_state->has_psr)

	if (!(crtc_state->has_psr || crtc_state->has_panel_replay))

		return;



	for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,