Commit 327e3012 authored by Vivek Kasireddy's avatar Vivek Kasireddy Committed by Lucas De Marchi
Browse files

drm/i915/xe2hpd: Identify the memory type for SKUs with GDDR + ECC 



Some SKUs of Xe2_HPD platforms (such as BMG) have GDDR memory type
with ECC enabled. We need to identify this scenario and add a new
case in xelpdp_get_dram_info() to handle it. In addition, the
derating value needs to be adjusted accordingly to compensate for
the limited bandwidth.

Bspec: 64602
Cc: Matt Roper <matthew.d.roper@intel.com>
Fixes: 3adcf970 ("drm/xe/bmg: Drop force_probe requirement")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarVivek Kasireddy <vivek.kasireddy@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Acked-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250324-tip-v2-1-38397de319f8@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent 11938353

drivers/gpu/drm/i915/display/intel_bw.c

+12 −0
Original line number Diff line number Diff line
@@ -250,6 +250,7 @@ static int icl_get_qgv_points(struct intel_display *display, 
			qi->deinterleave = 4;

			break;

		case INTEL_DRAM_GDDR:

		case INTEL_DRAM_GDDR_ECC:

			qi->channel_width = 32;

			break;

		default:
@@ -404,6 +405,12 @@ static const struct intel_sa_info xe2_hpd_sa_info = { 
	/* Other values not used by simplified algorithm */

};



static const struct intel_sa_info xe2_hpd_ecc_sa_info = {

	.derating = 45,

	.deprogbwlimit = 53,

	/* Other values not used by simplified algorithm */

};



static const struct intel_sa_info xe3lpd_sa_info = {

	.deburst = 32,

	.deprogbwlimit = 65, /* GB/s */
@@ -756,11 +763,16 @@ static unsigned int icl_qgv_bw(struct intel_display *display, 


void intel_bw_init_hw(struct intel_display *display)

{

	const struct dram_info *dram_info = &to_i915(display->drm)->dram_info;



	if (!HAS_DISPLAY(display))

		return;



	if (DISPLAY_VER(display) >= 30)

		tgl_get_bw_info(display, &xe3lpd_sa_info);

	else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx &&

		 dram_info->type == INTEL_DRAM_GDDR_ECC)

		xe2_hpd_get_bw_info(display, &xe2_hpd_ecc_sa_info);

	else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx)

		xe2_hpd_get_bw_info(display, &xe2_hpd_sa_info);

	else if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -305,6 +305,7 @@ struct drm_i915_private { 
			INTEL_DRAM_DDR5,

			INTEL_DRAM_LPDDR5,

			INTEL_DRAM_GDDR,

			INTEL_DRAM_GDDR_ECC,

		} type;

		u8 num_qgv_points;

		u8 num_psf_gv_points;

drivers/gpu/drm/i915/soc/intel_dram.c

+4 −0
Original line number Diff line number Diff line
@@ -687,6 +687,10 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915) 
		drm_WARN_ON(&i915->drm, !IS_DGFX(i915));

		dram_info->type = INTEL_DRAM_GDDR;

		break;

	case 9:

		drm_WARN_ON(&i915->drm, !IS_DGFX(i915));

		dram_info->type = INTEL_DRAM_GDDR_ECC;

		break;

	default:

		MISSING_CASE(val);

		return -EINVAL;

drivers/gpu/drm/xe/xe_device_types.h

+1 −0
Original line number Diff line number Diff line
@@ -575,6 +575,7 @@ struct xe_device { 
			INTEL_DRAM_DDR5,

			INTEL_DRAM_LPDDR5,

			INTEL_DRAM_GDDR,

			INTEL_DRAM_GDDR_ECC,

		} type;

		u8 num_qgv_points;

		u8 num_psf_gv_points;