Commit 328d35b7 authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/cpufeature' into for-next/core 

* for-next/cpufeature:
  arm64: cputype: Add cputype definition for HIP12
  arm64: Expose AIDR_EL1 via sysfs
  arm64/cpufeature: Add missing id_aa64mmfr4 feature reg update
parents 9bd2e7c6 226ff350

Documentation/ABI/testing/sysfs-devices-system-cpu

+1 −0
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@@ -485,6 +485,7 @@ What: /sys/devices/system/cpu/cpuX/regs/ 
		/sys/devices/system/cpu/cpuX/regs/identification/

		/sys/devices/system/cpu/cpuX/regs/identification/midr_el1

		/sys/devices/system/cpu/cpuX/regs/identification/revidr_el1

		/sys/devices/system/cpu/cpuX/regs/identification/aidr_el1

		/sys/devices/system/cpu/cpuX/regs/identification/smidr_el1

Date:		June 2016

Contact:	Linux ARM Kernel Mailing list <linux-arm-kernel@lists.infradead.org>

Documentation/arch/arm64/cpu-feature-registers.rst

+7 −6
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@@ -72,14 +72,15 @@ there are some issues with their usage. 
    process could be migrated to another CPU by the time it uses the

    register value, unless the CPU affinity is set. Hence, there is no

    guarantee that the value reflects the processor that it is

    currently executing on. The REVIDR is not exposed due to this

    constraint, as REVIDR makes sense only in conjunction with the

    MIDR. Alternately, MIDR_EL1 and REVIDR_EL1 are exposed via sysfs

    at::

    currently executing on. REVIDR and AIDR are not exposed due to this

    constraint, as these registers only make sense in conjunction with

    the MIDR. Alternately, MIDR_EL1, REVIDR_EL1, and AIDR_EL1 are exposed

    via sysfs at::



	/sys/devices/system/cpu/cpu$ID/regs/identification/

	                                              \- midr

	                                              \- revidr

	                                              \- midr_el1

	                                              \- revidr_el1

	                                              \- aidr_el1



3. Implementation

--------------------

arch/arm64/include/asm/cpu.h

+1 −0
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@@ -44,6 +44,7 @@ struct cpuinfo_arm64 { 
	u64		reg_dczid;

	u64		reg_midr;

	u64		reg_revidr;

	u64		reg_aidr;

	u64		reg_gmid;

	u64		reg_smidr;

	u64		reg_mpamidr;

arch/arm64/include/asm/cputype.h

+2 −0
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@@ -133,6 +133,7 @@ 


#define HISI_CPU_PART_TSV110		0xD01

#define HISI_CPU_PART_HIP09			0xD02

#define HISI_CPU_PART_HIP12		0xD06



#define APPLE_CPU_PART_M1_ICESTORM	0x022

#define APPLE_CPU_PART_M1_FIRESTORM	0x023
@@ -220,6 +221,7 @@ 
#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)

#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)

#define MIDR_HISI_HIP09 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP09)

#define MIDR_HISI_HIP12 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP12)

#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)

#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)

#define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)

arch/arm64/kernel/cpufeature.c

+2 −0
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@@ -1403,6 +1403,8 @@ void update_cpu_features(int cpu, 
				      info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);

	taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu,

				      info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3);

	taint |= check_update_ftr_reg(SYS_ID_AA64MMFR4_EL1, cpu,

				      info->reg_id_aa64mmfr4, boot->reg_id_aa64mmfr4);



	taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,

				      info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);