Commit 328d4a7e authored by Jerome Brunet's avatar Jerome Brunet
Browse files

clk: amlogic: remove unnecessary headers 

Some Amlogic clock controller drivers have a dedicated headers file, some
do not. Over time, these headers have evolved and now only carry register
offset definitions. These offsets are only used by the related controller
and are not meant to be shared.

These headers are not serving any purpose now.

Start enforcing some consistency between the different Amlogic clock
drivers and move the register offset definitions to the related driver.

Link: https://lore.kernel.org/r/20250623-clk-meson-no-headers-v1-1-468161a7279e@baylibre.com


[jbrunet: checkpatch strict: removed extra blank line]
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 301b96e0

drivers/clk/meson/a1-peripherals.c

+30 −1
Original line number Diff line number Diff line
@@ -10,13 +10,42 @@ 
#include <linux/clk-provider.h>

#include <linux/mod_devicetable.h>

#include <linux/platform_device.h>

#include "a1-peripherals.h"

#include "clk-dualdiv.h"

#include "clk-regmap.h"

#include "meson-clkc-utils.h"



#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>



#define SYS_OSCIN_CTRL		0x0

#define RTC_BY_OSCIN_CTRL0	0x4

#define RTC_BY_OSCIN_CTRL1	0x8

#define RTC_CTRL		0xc

#define SYS_CLK_CTRL0		0x10

#define SYS_CLK_EN0		0x1c

#define SYS_CLK_EN1		0x20

#define AXI_CLK_EN		0x24

#define DSPA_CLK_EN		0x28

#define DSPB_CLK_EN		0x2c

#define DSPA_CLK_CTRL0		0x30

#define DSPB_CLK_CTRL0		0x34

#define CLK12_24_CTRL		0x38

#define GEN_CLK_CTRL		0x3c

#define SAR_ADC_CLK_CTRL	0xc0

#define PWM_CLK_AB_CTRL		0xc4

#define PWM_CLK_CD_CTRL		0xc8

#define PWM_CLK_EF_CTRL		0xcc

#define SPICC_CLK_CTRL		0xd0

#define TS_CLK_CTRL		0xd4

#define SPIFC_CLK_CTRL		0xd8

#define USB_BUSCLK_CTRL		0xdc

#define SD_EMMC_CLK_CTRL	0xe0

#define CECA_CLK_CTRL0		0xe4

#define CECA_CLK_CTRL1		0xe8

#define CECB_CLK_CTRL0		0xec

#define CECB_CLK_CTRL1		0xf0

#define PSRAM_CLK_CTRL		0xf4

#define DMC_CLK_CTRL		0xf8



static struct clk_regmap xtal_in = {

	.data = &(struct clk_regmap_gate_data){

		.offset = SYS_OSCIN_CTRL,

drivers/clk/meson/a1-peripherals.h

deleted100644 → 0
+0 −46
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0+ */

/*

 * Amlogic A1 Peripherals Clock Controller internals

 *

 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.

 * Author: Jian Hu <jian.hu@amlogic.com>

 *

 * Copyright (c) 2023, SberDevices. All Rights Reserved.

 * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>

 */



#ifndef __A1_PERIPHERALS_H

#define __A1_PERIPHERALS_H



/* peripherals clock controller register offset */

#define SYS_OSCIN_CTRL		0x0

#define RTC_BY_OSCIN_CTRL0	0x4

#define RTC_BY_OSCIN_CTRL1	0x8

#define RTC_CTRL		0xc

#define SYS_CLK_CTRL0		0x10

#define SYS_CLK_EN0		0x1c

#define SYS_CLK_EN1		0x20

#define AXI_CLK_EN		0x24

#define DSPA_CLK_EN		0x28

#define DSPB_CLK_EN		0x2c

#define DSPA_CLK_CTRL0		0x30

#define DSPB_CLK_CTRL0		0x34

#define CLK12_24_CTRL		0x38

#define GEN_CLK_CTRL		0x3c

#define SAR_ADC_CLK_CTRL	0xc0

#define PWM_CLK_AB_CTRL		0xc4

#define PWM_CLK_CD_CTRL		0xc8

#define PWM_CLK_EF_CTRL		0xcc

#define SPICC_CLK_CTRL		0xd0

#define TS_CLK_CTRL		0xd4

#define SPIFC_CLK_CTRL		0xd8

#define USB_BUSCLK_CTRL		0xdc

#define SD_EMMC_CLK_CTRL	0xe0

#define CECA_CLK_CTRL0		0xe4

#define CECA_CLK_CTRL1		0xe8

#define CECB_CLK_CTRL0		0xec

#define CECB_CLK_CTRL1		0xf0

#define PSRAM_CLK_CTRL		0xf4

#define DMC_CLK_CTRL		0xf8



#endif /* __A1_PERIPHERALS_H */

drivers/clk/meson/a1-pll.c

+11 −1
Original line number Diff line number Diff line
@@ -10,10 +10,20 @@ 
#include <linux/clk-provider.h>

#include <linux/mod_devicetable.h>

#include <linux/platform_device.h>

#include "a1-pll.h"

#include "clk-pll.h"

#include "clk-regmap.h"

#include "meson-clkc-utils.h"



#define ANACTRL_FIXPLL_CTRL0	0x0

#define ANACTRL_FIXPLL_CTRL1	0x4

#define ANACTRL_FIXPLL_STS	0x14

#define ANACTRL_HIFIPLL_CTRL0	0xc0

#define ANACTRL_HIFIPLL_CTRL1	0xc4

#define ANACTRL_HIFIPLL_CTRL2	0xc8

#define ANACTRL_HIFIPLL_CTRL3	0xcc

#define ANACTRL_HIFIPLL_CTRL4	0xd0

#define ANACTRL_HIFIPLL_STS	0xd4



#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>



static struct clk_regmap fixed_pll_dco = {

drivers/clk/meson/a1-pll.h

deleted100644 → 0
+0 −28
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0+ */

/*

 * Amlogic A1 PLL Clock Controller internals

 *

 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.

 * Author: Jian Hu <jian.hu@amlogic.com>

 *

 * Copyright (c) 2023, SberDevices. All Rights Reserved.

 * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>

 */



#ifndef __A1_PLL_H

#define __A1_PLL_H



#include "clk-pll.h"



/* PLL register offset */

#define ANACTRL_FIXPLL_CTRL0	0x0

#define ANACTRL_FIXPLL_CTRL1	0x4

#define ANACTRL_FIXPLL_STS	0x14

#define ANACTRL_HIFIPLL_CTRL0	0xc0

#define ANACTRL_HIFIPLL_CTRL1	0xc4

#define ANACTRL_HIFIPLL_CTRL2	0xc8

#define ANACTRL_HIFIPLL_CTRL3	0xcc

#define ANACTRL_HIFIPLL_CTRL4	0xd0

#define ANACTRL_HIFIPLL_STS	0xd4



#endif /* __A1_PLL_H */

drivers/clk/meson/axg-audio.c

+55 −1
Original line number Diff line number Diff line
@@ -16,13 +16,67 @@ 
#include <linux/slab.h>



#include "meson-clkc-utils.h"

#include "axg-audio.h"

#include "clk-regmap.h"

#include "clk-phase.h"

#include "sclk-div.h"



#include <dt-bindings/clock/axg-audio-clkc.h>



/* Audio clock register offsets */

#define AUDIO_CLK_GATE_EN	0x000

#define AUDIO_MCLK_A_CTRL	0x004

#define AUDIO_MCLK_B_CTRL	0x008

#define AUDIO_MCLK_C_CTRL	0x00C

#define AUDIO_MCLK_D_CTRL	0x010

#define AUDIO_MCLK_E_CTRL	0x014

#define AUDIO_MCLK_F_CTRL	0x018

#define AUDIO_MST_PAD_CTRL0	0x01c

#define AUDIO_MST_PAD_CTRL1	0x020

#define AUDIO_SW_RESET		0x024

#define AUDIO_MST_A_SCLK_CTRL0	0x040

#define AUDIO_MST_A_SCLK_CTRL1	0x044

#define AUDIO_MST_B_SCLK_CTRL0	0x048

#define AUDIO_MST_B_SCLK_CTRL1	0x04C

#define AUDIO_MST_C_SCLK_CTRL0	0x050

#define AUDIO_MST_C_SCLK_CTRL1	0x054

#define AUDIO_MST_D_SCLK_CTRL0	0x058

#define AUDIO_MST_D_SCLK_CTRL1	0x05C

#define AUDIO_MST_E_SCLK_CTRL0	0x060

#define AUDIO_MST_E_SCLK_CTRL1	0x064

#define AUDIO_MST_F_SCLK_CTRL0	0x068

#define AUDIO_MST_F_SCLK_CTRL1	0x06C

#define AUDIO_CLK_TDMIN_A_CTRL	0x080

#define AUDIO_CLK_TDMIN_B_CTRL	0x084

#define AUDIO_CLK_TDMIN_C_CTRL	0x088

#define AUDIO_CLK_TDMIN_LB_CTRL 0x08C

#define AUDIO_CLK_TDMOUT_A_CTRL 0x090

#define AUDIO_CLK_TDMOUT_B_CTRL 0x094

#define AUDIO_CLK_TDMOUT_C_CTRL 0x098

#define AUDIO_CLK_SPDIFIN_CTRL	0x09C

#define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0

#define AUDIO_CLK_RESAMPLE_CTRL 0x0A4

#define AUDIO_CLK_LOCKER_CTRL	0x0A8

#define AUDIO_CLK_PDMIN_CTRL0	0x0AC

#define AUDIO_CLK_PDMIN_CTRL1	0x0B0

#define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4



/* SM1 introduce new register and some shifts :( */

#define AUDIO_CLK_GATE_EN1	0x004

#define AUDIO_SM1_MCLK_A_CTRL	0x008

#define AUDIO_SM1_MCLK_B_CTRL	0x00C

#define AUDIO_SM1_MCLK_C_CTRL	0x010

#define AUDIO_SM1_MCLK_D_CTRL	0x014

#define AUDIO_SM1_MCLK_E_CTRL	0x018

#define AUDIO_SM1_MCLK_F_CTRL	0x01C

#define AUDIO_SM1_MST_PAD_CTRL0	0x020

#define AUDIO_SM1_MST_PAD_CTRL1	0x024

#define AUDIO_SM1_SW_RESET0	0x028

#define AUDIO_SM1_SW_RESET1	0x02C

#define AUDIO_CLK81_CTRL	0x030

#define AUDIO_CLK81_EN		0x034

#define AUDIO_EARCRX_CMDC_CLK_CTRL	0x0D0

#define AUDIO_EARCRX_DMAC_CLK_CTRL	0x0D4



#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) {			\

	.data = &(struct clk_regmap_gate_data){				\

		.offset = (_reg),					\