Commit 328e089b authored by Balasubramani Vivekanandan's avatar Balasubramani Vivekanandan Committed by Rodrigo Vivi
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drm/xe: Leverage ComputeCS read L3 caching 



On platforms that support read L3 caching, set the default mocs index in
CCS RING_CMD_CTL to leverage the read caching in L3.

Currently PVC and Xe2 platforms have the support.

Bspec: 72161
Signed-off-by: default avatarBalasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230929051539.3157441-1-lucas.demarchi@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 30603b5b

drivers/gpu/drm/xe/xe_hw_engine.c

+14 −11
Original line number Diff line number Diff line
@@ -316,13 +316,7 @@ static void 
hw_engine_setup_default_state(struct xe_hw_engine *hwe)

{

	struct xe_gt *gt = hwe->gt;

	const u8 mocs_write_idx = gt->mocs.uc_index;

	/* TODO: missing handling of HAS_L3_CCS_READ platforms */

	const u8 mocs_read_idx = gt->mocs.uc_index;

	u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) |

				REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx);

	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);

	const struct xe_rtp_entry_sr engine_entries[] = {

	struct xe_device *xe = gt_to_xe(gt);

	/*

	 * RING_CMD_CCTL specifies the default MOCS entry that will be

	 * used by the command streamer when executing commands that
@@ -331,7 +325,16 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe) 
	 * corresponds to uncached behavior, although use of a WB cached

	 * entry is recommended by the spec in certain circumstances on

	 * specific platforms.

	 * Bspec: 72161

	 */

	const u8 mocs_write_idx = gt->mocs.uc_index;

	const u8 mocs_read_idx = hwe->class == XE_ENGINE_CLASS_COMPUTE &&

				 (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) ?

				 gt->mocs.wb_index : gt->mocs.uc_index;

	u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) |

				REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx);

	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);

	const struct xe_rtp_entry_sr engine_entries[] = {

		{ XE_RTP_NAME("RING_CMD_CCTL_default_MOCS"),

		  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED)),

		  XE_RTP_ACTIONS(FIELD_SET(RING_CMD_CCTL(0),